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Searched refs:type1 (Results 1 – 6 of 6) sorted by relevance

/dev/bus/pci/
A Dpci.cpp227 config->type1.primary_bus = read_byte(); if (err < 0) return err; in pci_read_config()
228 config->type1.secondary_bus = read_byte(); if (err < 0) return err; in pci_read_config()
231 config->type1.io_base = read_byte(); if (err < 0) return err; in pci_read_config()
232 config->type1.io_limit = read_byte(); if (err < 0) return err; in pci_read_config()
234 config->type1.memory_base = read_half(); if (err < 0) return err; in pci_read_config()
235 config->type1.memory_limit = read_half(); if (err < 0) return err; in pci_read_config()
240 config->type1.io_base_upper = read_half(); if (err < 0) return err; in pci_read_config()
241 config->type1.io_limit_upper = read_half(); if (err < 0) return err; in pci_read_config()
245 config->type1.interrupt_line = read_byte(); if (err < 0) return err; in pci_read_config()
246 config->type1.interrupt_pin = read_byte(); if (err < 0) return err; in pci_read_config()
[all …]
A Ddebug.cpp123 … config.type1.primary_bus, config.type1.secondary_bus, config.type1.subordinate_bus); in pci_config()
126 i+1, config.type1.base_addresses[i+1]); in pci_config()
128 printf("mem base=%08x mem limit=%08x\n", config.type1.memory_base << 16, in pci_config()
129 (config.type1.memory_limit << 16) | 0xf'ffff); in pci_config()
130 switch ((config.type1.io_base & 0xf)) { in pci_config()
133 ((config.type1.io_limit & 0xf0) << 8) | 0xfff ); in pci_config()
137 (config.type1.io_base % 0xf0) << 8 | config.type1.io_base_upper << 16, in pci_config()
138 … ((config.type1.io_limit & 0xf0) << 8) | 0xfff | config.type1.io_limit_upper << 16); in pci_config()
141 switch ((config.type1.prefetchable_memory_base & 0xf)) { in pci_config()
144 (config.type1.prefetchable_memory_base & 0xfff0) << 16, in pci_config()
[all …]
A Drules.mk16 MODULE_SRCS += $(LOCAL_DIR)/backend/type1.cpp
/dev/bus/pci/bus_mgr/
A Dbridge.cpp204 if (config_.type1.io_limit < config_.type1.io_base) { in io_range()
208 return { ((uint32_t)config_.type1.io_base >> 4) << 12, in io_range()
209 (((uint32_t)config_.type1.io_limit >> 4) << 12) | 0xfff }; in io_range()
214 if (config_.type1.memory_limit < config_.type1.memory_base) { in mem_range()
217 return { ((uint32_t)config_.type1.memory_base >> 4) << 20, in mem_range()
223 if (config_.type1.prefetchable_memory_limit < config_.type1.prefetchable_memory_base) { in prefetch_range()
226 bool is_64 = (config_.type1.prefetchable_memory_base & 0xf) == 1; in prefetch_range()
230 base = (((uint64_t)config_.type1.prefetchable_memory_base >> 4) << 20); in prefetch_range()
232 base |= (uint64_t)config_.type1.prefetchable_base_upper << 32; in prefetch_range()
236 limit |= (uint64_t)config_.type1.prefetchable_limit_upper << 32; in prefetch_range()
[all …]
A Dbridge.h48 uint8_t primary_bus() const { return config_.type1.primary_bus; } in primary_bus()
49 uint8_t secondary_bus() const { return config_.type1.secondary_bus; } in secondary_bus()
50 uint8_t subordinate_bus() const { return config_.type1.subordinate_bus; } in subordinate_bus()
/dev/include/hw/
A Dpci.h142 } type1; // configuration for bridge devices member

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