1 //***************************************************************************** 2 // 3 // hw_adc.h - Macros used when accessing the ADC hardware. 4 // 5 // Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_ADC_H__ 41 #define __HW_ADC_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the ADC register offsets. 46 // 47 //***************************************************************************** 48 #define ADC_O_ACTSS 0x00000000 // ADC Active Sample Sequencer 49 #define ADC_O_RIS 0x00000004 // ADC Raw Interrupt Status 50 #define ADC_O_IM 0x00000008 // ADC Interrupt Mask 51 #define ADC_O_ISC 0x0000000C // ADC Interrupt Status and Clear 52 #define ADC_O_OSTAT 0x00000010 // ADC Overflow Status 53 #define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select 54 #define ADC_O_USTAT 0x00000018 // ADC Underflow Status 55 #define ADC_O_TSSEL 0x0000001C // ADC Trigger Source Select 56 #define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority 57 #define ADC_O_SPC 0x00000024 // ADC Sample Phase Control 58 #define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence 59 // Initiate 60 #define ADC_O_SAC 0x00000030 // ADC Sample Averaging Control 61 #define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt 62 // Status and Clear 63 #define ADC_O_CTL 0x00000038 // ADC Control 64 #define ADC_O_SSMUX0 0x00000040 // ADC Sample Sequence Input 65 // Multiplexer Select 0 66 #define ADC_O_SSCTL0 0x00000044 // ADC Sample Sequence Control 0 67 #define ADC_O_SSFIFO0 0x00000048 // ADC Sample Sequence Result FIFO 68 // 0 69 #define ADC_O_SSFSTAT0 0x0000004C // ADC Sample Sequence FIFO 0 70 // Status 71 #define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation 72 #define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital 73 // Comparator Select 74 #define ADC_O_SSEMUX0 0x00000058 // ADC Sample Sequence Extended 75 // Input Multiplexer Select 0 76 #define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input 77 // Multiplexer Select 1 78 #define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1 79 #define ADC_O_SSFIFO1 0x00000068 // ADC Sample Sequence Result FIFO 80 // 1 81 #define ADC_O_SSFSTAT1 0x0000006C // ADC Sample Sequence FIFO 1 82 // Status 83 #define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation 84 #define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital 85 // Comparator Select 86 #define ADC_O_SSEMUX1 0x00000078 // ADC Sample Sequence Extended 87 // Input Multiplexer Select 1 88 #define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input 89 // Multiplexer Select 2 90 #define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2 91 #define ADC_O_SSFIFO2 0x00000088 // ADC Sample Sequence Result FIFO 92 // 2 93 #define ADC_O_SSFSTAT2 0x0000008C // ADC Sample Sequence FIFO 2 94 // Status 95 #define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation 96 #define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital 97 // Comparator Select 98 #define ADC_O_SSEMUX2 0x00000098 // ADC Sample Sequence Extended 99 // Input Multiplexer Select 2 100 #define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input 101 // Multiplexer Select 3 102 #define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3 103 #define ADC_O_SSFIFO3 0x000000A8 // ADC Sample Sequence Result FIFO 104 // 3 105 #define ADC_O_SSFSTAT3 0x000000AC // ADC Sample Sequence FIFO 3 106 // Status 107 #define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation 108 #define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital 109 // Comparator Select 110 #define ADC_O_SSEMUX3 0x000000B8 // ADC Sample Sequence Extended 111 // Input Multiplexer Select 3 112 #define ADC_O_TMLB 0x00000100 // ADC Test Mode Loopback 113 #define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset 114 // Initial Conditions 115 #define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0 116 #define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1 117 #define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2 118 #define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3 119 #define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4 120 #define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5 121 #define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6 122 #define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7 123 #define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0 124 #define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1 125 #define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2 126 #define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3 127 #define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4 128 #define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5 129 #define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6 130 #define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7 131 #define ADC_O_PP 0x00000FC0 // ADC Peripheral Properties 132 #define ADC_O_PC 0x00000FC4 // ADC Peripheral Configuration 133 #define ADC_O_CC 0x00000FC8 // ADC Clock Configuration 134 135 //***************************************************************************** 136 // 137 // The following are defines for the bit fields in the ADC_O_ACTSS register. 138 // 139 //***************************************************************************** 140 #define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable 141 #define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable 142 #define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable 143 #define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable 144 145 //***************************************************************************** 146 // 147 // The following are defines for the bit fields in the ADC_O_RIS register. 148 // 149 //***************************************************************************** 150 #define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt 151 // Status 152 #define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status 153 #define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status 154 #define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status 155 #define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status 156 157 //***************************************************************************** 158 // 159 // The following are defines for the bit fields in the ADC_O_IM register. 160 // 161 //***************************************************************************** 162 #define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on 163 // SS3 164 #define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on 165 // SS2 166 #define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on 167 // SS1 168 #define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on 169 // SS0 170 #define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask 171 #define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask 172 #define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask 173 #define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask 174 175 //***************************************************************************** 176 // 177 // The following are defines for the bit fields in the ADC_O_ISC register. 178 // 179 //***************************************************************************** 180 #define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt 181 // Status on SS3 182 #define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt 183 // Status on SS2 184 #define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt 185 // Status on SS1 186 #define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt 187 // Status on SS0 188 #define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear 189 #define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear 190 #define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear 191 #define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear 192 193 //***************************************************************************** 194 // 195 // The following are defines for the bit fields in the ADC_O_OSTAT register. 196 // 197 //***************************************************************************** 198 #define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow 199 #define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow 200 #define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow 201 #define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow 202 203 //***************************************************************************** 204 // 205 // The following are defines for the bit fields in the ADC_O_EMUX register. 206 // 207 //***************************************************************************** 208 #define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select 209 #define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) 210 #define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 211 #define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 212 #define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2 213 #define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4) 214 #define ADC_EMUX_EM3_TIMER 0x00005000 // Timer 215 #define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 216 #define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 217 #define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 218 #define ADC_EMUX_EM3_PWM3 0x00009000 // PWM3 219 #define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) 220 #define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select 221 #define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) 222 #define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 223 #define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 224 #define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2 225 #define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4) 226 #define ADC_EMUX_EM2_TIMER 0x00000500 // Timer 227 #define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 228 #define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 229 #define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 230 #define ADC_EMUX_EM2_PWM3 0x00000900 // PWM3 231 #define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) 232 #define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select 233 #define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) 234 #define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 235 #define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 236 #define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2 237 #define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4) 238 #define ADC_EMUX_EM1_TIMER 0x00000050 // Timer 239 #define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 240 #define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 241 #define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 242 #define ADC_EMUX_EM1_PWM3 0x00000090 // PWM3 243 #define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) 244 #define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select 245 #define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) 246 #define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 247 #define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 248 #define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2 249 #define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4) 250 #define ADC_EMUX_EM0_TIMER 0x00000005 // Timer 251 #define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 252 #define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 253 #define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 254 #define ADC_EMUX_EM0_PWM3 0x00000009 // PWM3 255 #define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) 256 257 //***************************************************************************** 258 // 259 // The following are defines for the bit fields in the ADC_O_USTAT register. 260 // 261 //***************************************************************************** 262 #define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow 263 #define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow 264 #define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow 265 #define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow 266 267 //***************************************************************************** 268 // 269 // The following are defines for the bit fields in the ADC_O_TSSEL register. 270 // 271 //***************************************************************************** 272 #define ADC_TSSEL_PS3_M 0x30000000 // PWM Unit Select 273 #define ADC_TSSEL_PS3_0 0x00000000 // PWM Unit 0 274 #define ADC_TSSEL_PS3_1 0x10000000 // PWM Unit 1 275 #define ADC_TSSEL_PS2_M 0x00300000 // PWM Unit Select 276 #define ADC_TSSEL_PS2_0 0x00000000 // PWM Unit 0 277 #define ADC_TSSEL_PS2_1 0x00100000 // PWM Unit 1 278 #define ADC_TSSEL_PS1_M 0x00003000 // PWM Unit Select 279 #define ADC_TSSEL_PS1_0 0x00000000 // PWM Unit 0 280 #define ADC_TSSEL_PS1_1 0x00001000 // PWM Unit 1 281 #define ADC_TSSEL_PS0_M 0x00000030 // PWM Unit Select 282 #define ADC_TSSEL_PS0_0 0x00000000 // PWM Unit 0 283 #define ADC_TSSEL_PS0_1 0x00000010 // PWM Unit 1 284 285 //***************************************************************************** 286 // 287 // The following are defines for the bit fields in the ADC_O_SSPRI register. 288 // 289 //***************************************************************************** 290 #define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority 291 #define ADC_SSPRI_SS3_1ST 0x00000000 // First priority 292 #define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority 293 #define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority 294 #define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority 295 #define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority 296 #define ADC_SSPRI_SS2_1ST 0x00000000 // First priority 297 #define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority 298 #define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority 299 #define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority 300 #define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority 301 #define ADC_SSPRI_SS1_1ST 0x00000000 // First priority 302 #define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority 303 #define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority 304 #define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority 305 #define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority 306 #define ADC_SSPRI_SS0_1ST 0x00000000 // First priority 307 #define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority 308 #define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority 309 #define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority 310 311 //***************************************************************************** 312 // 313 // The following are defines for the bit fields in the ADC_O_SPC register. 314 // 315 //***************************************************************************** 316 #define ADC_SPC_PHASE_M 0x0000000F // Phase Difference 317 #define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 318 #define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 319 #define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 320 #define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 321 #define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 322 #define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 323 #define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 324 #define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 325 #define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 326 #define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 327 #define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 328 #define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 329 #define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 330 #define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 331 #define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 332 #define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 333 334 //***************************************************************************** 335 // 336 // The following are defines for the bit fields in the ADC_O_PSSI register. 337 // 338 //***************************************************************************** 339 #define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize 340 #define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait 341 #define ADC_PSSI_SS3 0x00000008 // SS3 Initiate 342 #define ADC_PSSI_SS2 0x00000004 // SS2 Initiate 343 #define ADC_PSSI_SS1 0x00000002 // SS1 Initiate 344 #define ADC_PSSI_SS0 0x00000001 // SS0 Initiate 345 346 //***************************************************************************** 347 // 348 // The following are defines for the bit fields in the ADC_O_SAC register. 349 // 350 //***************************************************************************** 351 #define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control 352 #define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling 353 #define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling 354 #define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling 355 #define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling 356 #define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling 357 #define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling 358 #define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling 359 360 //***************************************************************************** 361 // 362 // The following are defines for the bit fields in the ADC_O_DCISC register. 363 // 364 //***************************************************************************** 365 #define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt 366 // Status and Clear 367 #define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt 368 // Status and Clear 369 #define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt 370 // Status and Clear 371 #define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt 372 // Status and Clear 373 #define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt 374 // Status and Clear 375 #define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt 376 // Status and Clear 377 #define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt 378 // Status and Clear 379 #define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt 380 // Status and Clear 381 382 //***************************************************************************** 383 // 384 // The following are defines for the bit fields in the ADC_O_CTL register. 385 // 386 //***************************************************************************** 387 #define ADC_CTL_RES 0x00000010 // Sample Resolution 388 #define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select 389 #define ADC_CTL_VREF_INTERNAL 0x00000000 // The internal reference as the 390 // voltage reference 391 #define ADC_CTL_VREF_EXT_3V 0x00000001 // A 3.0 V external VREFA input is 392 // the voltage reference. The ADC 393 // conversion range is 0.0 V to the 394 // external reference value 395 #define ADC_CTL_VREF_EXT_1V 0x00000003 // A 1.0 V external VREFA input is 396 // the voltage reference. The ADC 397 // conversion range is 0.0 V to 398 // three times the external 399 // reference value 400 #define ADC_CTL_VREF 0x00000001 // Voltage Reference Select 401 402 //***************************************************************************** 403 // 404 // The following are defines for the bit fields in the ADC_O_SSMUX0 register. 405 // 406 //***************************************************************************** 407 #define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select 408 #define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select 409 #define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select 410 #define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select 411 #define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select 412 #define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select 413 #define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select 414 #define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select 415 #define ADC_SSMUX0_MUX7_S 28 416 #define ADC_SSMUX0_MUX6_S 24 417 #define ADC_SSMUX0_MUX5_S 20 418 #define ADC_SSMUX0_MUX4_S 16 419 #define ADC_SSMUX0_MUX3_S 12 420 #define ADC_SSMUX0_MUX2_S 8 421 #define ADC_SSMUX0_MUX1_S 4 422 #define ADC_SSMUX0_MUX0_S 0 423 424 //***************************************************************************** 425 // 426 // The following are defines for the bit fields in the ADC_O_SSCTL0 register. 427 // 428 //***************************************************************************** 429 #define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select 430 #define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable 431 #define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence 432 #define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select 433 #define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select 434 #define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable 435 #define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence 436 #define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select 437 #define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select 438 #define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable 439 #define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence 440 #define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select 441 #define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select 442 #define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable 443 #define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence 444 #define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select 445 #define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select 446 #define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable 447 #define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence 448 #define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select 449 #define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select 450 #define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable 451 #define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence 452 #define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select 453 #define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select 454 #define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable 455 #define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence 456 #define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select 457 #define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select 458 #define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable 459 #define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence 460 #define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select 461 462 //***************************************************************************** 463 // 464 // The following are defines for the bit fields in the ADC_O_SSFIFO0 register. 465 // 466 //***************************************************************************** 467 #define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data 468 #define ADC_SSFIFO0_DATA_S 0 469 470 //***************************************************************************** 471 // 472 // The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. 473 // 474 //***************************************************************************** 475 #define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full 476 #define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty 477 #define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer 478 #define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer 479 #define ADC_SSFSTAT0_HPTR_S 4 480 #define ADC_SSFSTAT0_TPTR_S 0 481 482 //***************************************************************************** 483 // 484 // The following are defines for the bit fields in the ADC_O_SSOP0 register. 485 // 486 //***************************************************************************** 487 #define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator 488 // Operation 489 #define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator 490 // Operation 491 #define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator 492 // Operation 493 #define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator 494 // Operation 495 #define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator 496 // Operation 497 #define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator 498 // Operation 499 #define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator 500 // Operation 501 #define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator 502 // Operation 503 504 //***************************************************************************** 505 // 506 // The following are defines for the bit fields in the ADC_O_SSDC0 register. 507 // 508 //***************************************************************************** 509 #define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator 510 // Select 511 #define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator 512 // Select 513 #define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator 514 // Select 515 #define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator 516 // Select 517 #define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator 518 // Select 519 #define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator 520 // Select 521 #define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator 522 // Select 523 #define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator 524 // Select 525 #define ADC_SSDC0_S6DCSEL_S 24 526 #define ADC_SSDC0_S5DCSEL_S 20 527 #define ADC_SSDC0_S4DCSEL_S 16 528 #define ADC_SSDC0_S3DCSEL_S 12 529 #define ADC_SSDC0_S2DCSEL_S 8 530 #define ADC_SSDC0_S1DCSEL_S 4 531 #define ADC_SSDC0_S0DCSEL_S 0 532 533 //***************************************************************************** 534 // 535 // The following are defines for the bit fields in the ADC_O_SSEMUX0 register. 536 // 537 //***************************************************************************** 538 #define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper 539 // Bit) 540 #define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper 541 // Bit) 542 #define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper 543 // Bit) 544 #define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper 545 // Bit) 546 #define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper 547 // Bit) 548 #define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper 549 // Bit) 550 #define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper 551 // Bit) 552 #define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper 553 // Bit) 554 555 //***************************************************************************** 556 // 557 // The following are defines for the bit fields in the ADC_O_SSMUX1 register. 558 // 559 //***************************************************************************** 560 #define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select 561 #define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select 562 #define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select 563 #define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select 564 #define ADC_SSMUX1_MUX3_S 12 565 #define ADC_SSMUX1_MUX2_S 8 566 #define ADC_SSMUX1_MUX1_S 4 567 #define ADC_SSMUX1_MUX0_S 0 568 569 //***************************************************************************** 570 // 571 // The following are defines for the bit fields in the ADC_O_SSCTL1 register. 572 // 573 //***************************************************************************** 574 #define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select 575 #define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable 576 #define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence 577 #define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select 578 #define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select 579 #define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable 580 #define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence 581 #define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select 582 #define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select 583 #define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable 584 #define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence 585 #define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select 586 #define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select 587 #define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable 588 #define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence 589 #define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select 590 591 //***************************************************************************** 592 // 593 // The following are defines for the bit fields in the ADC_O_SSFIFO1 register. 594 // 595 //***************************************************************************** 596 #define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data 597 #define ADC_SSFIFO1_DATA_S 0 598 599 //***************************************************************************** 600 // 601 // The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. 602 // 603 //***************************************************************************** 604 #define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full 605 #define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty 606 #define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer 607 #define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer 608 #define ADC_SSFSTAT1_HPTR_S 4 609 #define ADC_SSFSTAT1_TPTR_S 0 610 611 //***************************************************************************** 612 // 613 // The following are defines for the bit fields in the ADC_O_SSOP1 register. 614 // 615 //***************************************************************************** 616 #define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator 617 // Operation 618 #define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator 619 // Operation 620 #define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator 621 // Operation 622 #define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator 623 // Operation 624 625 //***************************************************************************** 626 // 627 // The following are defines for the bit fields in the ADC_O_SSDC1 register. 628 // 629 //***************************************************************************** 630 #define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator 631 // Select 632 #define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator 633 // Select 634 #define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator 635 // Select 636 #define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator 637 // Select 638 #define ADC_SSDC1_S2DCSEL_S 8 639 #define ADC_SSDC1_S1DCSEL_S 4 640 #define ADC_SSDC1_S0DCSEL_S 0 641 642 //***************************************************************************** 643 // 644 // The following are defines for the bit fields in the ADC_O_SSEMUX1 register. 645 // 646 //***************************************************************************** 647 #define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper 648 // Bit) 649 #define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper 650 // Bit) 651 #define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper 652 // Bit) 653 #define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper 654 // Bit) 655 656 //***************************************************************************** 657 // 658 // The following are defines for the bit fields in the ADC_O_SSMUX2 register. 659 // 660 //***************************************************************************** 661 #define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select 662 #define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select 663 #define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select 664 #define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select 665 #define ADC_SSMUX2_MUX3_S 12 666 #define ADC_SSMUX2_MUX2_S 8 667 #define ADC_SSMUX2_MUX1_S 4 668 #define ADC_SSMUX2_MUX0_S 0 669 670 //***************************************************************************** 671 // 672 // The following are defines for the bit fields in the ADC_O_SSCTL2 register. 673 // 674 //***************************************************************************** 675 #define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select 676 #define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable 677 #define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence 678 #define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select 679 #define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select 680 #define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable 681 #define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence 682 #define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select 683 #define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select 684 #define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable 685 #define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence 686 #define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select 687 #define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select 688 #define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable 689 #define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence 690 #define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select 691 692 //***************************************************************************** 693 // 694 // The following are defines for the bit fields in the ADC_O_SSFIFO2 register. 695 // 696 //***************************************************************************** 697 #define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data 698 #define ADC_SSFIFO2_DATA_S 0 699 700 //***************************************************************************** 701 // 702 // The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. 703 // 704 //***************************************************************************** 705 #define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full 706 #define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty 707 #define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer 708 #define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer 709 #define ADC_SSFSTAT2_HPTR_S 4 710 #define ADC_SSFSTAT2_TPTR_S 0 711 712 //***************************************************************************** 713 // 714 // The following are defines for the bit fields in the ADC_O_SSOP2 register. 715 // 716 //***************************************************************************** 717 #define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator 718 // Operation 719 #define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator 720 // Operation 721 #define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator 722 // Operation 723 #define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator 724 // Operation 725 726 //***************************************************************************** 727 // 728 // The following are defines for the bit fields in the ADC_O_SSDC2 register. 729 // 730 //***************************************************************************** 731 #define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator 732 // Select 733 #define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator 734 // Select 735 #define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator 736 // Select 737 #define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator 738 // Select 739 #define ADC_SSDC2_S2DCSEL_S 8 740 #define ADC_SSDC2_S1DCSEL_S 4 741 #define ADC_SSDC2_S0DCSEL_S 0 742 743 //***************************************************************************** 744 // 745 // The following are defines for the bit fields in the ADC_O_SSEMUX2 register. 746 // 747 //***************************************************************************** 748 #define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper 749 // Bit) 750 #define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper 751 // Bit) 752 #define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper 753 // Bit) 754 #define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper 755 // Bit) 756 757 //***************************************************************************** 758 // 759 // The following are defines for the bit fields in the ADC_O_SSMUX3 register. 760 // 761 //***************************************************************************** 762 #define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select 763 #define ADC_SSMUX3_MUX0_S 0 764 765 //***************************************************************************** 766 // 767 // The following are defines for the bit fields in the ADC_O_SSCTL3 register. 768 // 769 //***************************************************************************** 770 #define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select 771 #define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable 772 #define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence 773 #define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select 774 775 //***************************************************************************** 776 // 777 // The following are defines for the bit fields in the ADC_O_SSFIFO3 register. 778 // 779 //***************************************************************************** 780 #define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data 781 #define ADC_SSFIFO3_DATA_S 0 782 783 //***************************************************************************** 784 // 785 // The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. 786 // 787 //***************************************************************************** 788 #define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full 789 #define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty 790 #define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer 791 #define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer 792 #define ADC_SSFSTAT3_HPTR_S 4 793 #define ADC_SSFSTAT3_TPTR_S 0 794 795 //***************************************************************************** 796 // 797 // The following are defines for the bit fields in the ADC_O_SSOP3 register. 798 // 799 //***************************************************************************** 800 #define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator 801 // Operation 802 803 //***************************************************************************** 804 // 805 // The following are defines for the bit fields in the ADC_O_SSDC3 register. 806 // 807 //***************************************************************************** 808 #define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator 809 // Select 810 811 //***************************************************************************** 812 // 813 // The following are defines for the bit fields in the ADC_O_SSEMUX3 register. 814 // 815 //***************************************************************************** 816 #define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper 817 // Bit) 818 819 //***************************************************************************** 820 // 821 // The following are defines for the bit fields in the ADC_O_TMLB register. 822 // 823 //***************************************************************************** 824 #define ADC_TMLB_LB 0x00000001 // Loopback Mode Enable 825 826 //***************************************************************************** 827 // 828 // The following are defines for the bit fields in the ADC_O_DCRIC register. 829 // 830 //***************************************************************************** 831 #define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 832 #define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 833 #define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 834 #define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 835 #define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 836 #define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 837 #define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 838 #define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 839 #define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 840 #define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 841 #define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 842 #define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 843 #define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 844 #define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 845 #define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 846 #define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 847 848 //***************************************************************************** 849 // 850 // The following are defines for the bit fields in the ADC_O_DCCTL0 register. 851 // 852 //***************************************************************************** 853 #define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable 854 #define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition 855 #define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band 856 #define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band 857 #define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band 858 #define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode 859 #define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always 860 #define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once 861 #define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always 862 #define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once 863 #define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable 864 #define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition 865 #define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band 866 #define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band 867 #define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band 868 #define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode 869 #define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always 870 #define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once 871 #define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always 872 #define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once 873 874 //***************************************************************************** 875 // 876 // The following are defines for the bit fields in the ADC_O_DCCTL1 register. 877 // 878 //***************************************************************************** 879 #define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable 880 #define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition 881 #define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band 882 #define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band 883 #define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band 884 #define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode 885 #define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always 886 #define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once 887 #define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always 888 #define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once 889 #define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable 890 #define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition 891 #define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band 892 #define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band 893 #define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band 894 #define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode 895 #define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always 896 #define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once 897 #define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always 898 #define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once 899 900 //***************************************************************************** 901 // 902 // The following are defines for the bit fields in the ADC_O_DCCTL2 register. 903 // 904 //***************************************************************************** 905 #define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable 906 #define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition 907 #define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band 908 #define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band 909 #define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band 910 #define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode 911 #define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always 912 #define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once 913 #define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always 914 #define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once 915 #define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable 916 #define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition 917 #define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band 918 #define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band 919 #define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band 920 #define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode 921 #define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always 922 #define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once 923 #define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always 924 #define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once 925 926 //***************************************************************************** 927 // 928 // The following are defines for the bit fields in the ADC_O_DCCTL3 register. 929 // 930 //***************************************************************************** 931 #define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable 932 #define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition 933 #define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band 934 #define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band 935 #define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band 936 #define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode 937 #define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always 938 #define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once 939 #define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always 940 #define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once 941 #define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable 942 #define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition 943 #define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band 944 #define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band 945 #define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band 946 #define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode 947 #define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always 948 #define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once 949 #define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always 950 #define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once 951 952 //***************************************************************************** 953 // 954 // The following are defines for the bit fields in the ADC_O_DCCTL4 register. 955 // 956 //***************************************************************************** 957 #define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable 958 #define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition 959 #define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band 960 #define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band 961 #define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band 962 #define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode 963 #define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always 964 #define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once 965 #define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always 966 #define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once 967 #define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable 968 #define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition 969 #define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band 970 #define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band 971 #define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band 972 #define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode 973 #define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always 974 #define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once 975 #define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always 976 #define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once 977 978 //***************************************************************************** 979 // 980 // The following are defines for the bit fields in the ADC_O_DCCTL5 register. 981 // 982 //***************************************************************************** 983 #define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable 984 #define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition 985 #define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band 986 #define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band 987 #define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band 988 #define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode 989 #define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always 990 #define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once 991 #define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always 992 #define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once 993 #define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable 994 #define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition 995 #define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band 996 #define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band 997 #define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band 998 #define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode 999 #define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always 1000 #define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once 1001 #define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always 1002 #define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once 1003 1004 //***************************************************************************** 1005 // 1006 // The following are defines for the bit fields in the ADC_O_DCCTL6 register. 1007 // 1008 //***************************************************************************** 1009 #define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable 1010 #define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition 1011 #define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band 1012 #define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band 1013 #define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band 1014 #define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode 1015 #define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always 1016 #define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once 1017 #define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always 1018 #define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once 1019 #define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable 1020 #define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition 1021 #define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band 1022 #define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band 1023 #define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band 1024 #define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode 1025 #define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always 1026 #define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once 1027 #define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always 1028 #define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once 1029 1030 //***************************************************************************** 1031 // 1032 // The following are defines for the bit fields in the ADC_O_DCCTL7 register. 1033 // 1034 //***************************************************************************** 1035 #define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable 1036 #define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition 1037 #define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band 1038 #define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band 1039 #define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band 1040 #define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode 1041 #define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always 1042 #define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once 1043 #define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always 1044 #define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once 1045 #define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable 1046 #define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition 1047 #define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band 1048 #define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band 1049 #define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band 1050 #define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode 1051 #define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always 1052 #define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once 1053 #define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always 1054 #define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once 1055 1056 //***************************************************************************** 1057 // 1058 // The following are defines for the bit fields in the ADC_O_DCCMP0 register. 1059 // 1060 //***************************************************************************** 1061 #define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 1062 #define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 1063 #define ADC_DCCMP0_COMP1_S 16 1064 #define ADC_DCCMP0_COMP0_S 0 1065 1066 //***************************************************************************** 1067 // 1068 // The following are defines for the bit fields in the ADC_O_DCCMP1 register. 1069 // 1070 //***************************************************************************** 1071 #define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 1072 #define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 1073 #define ADC_DCCMP1_COMP1_S 16 1074 #define ADC_DCCMP1_COMP0_S 0 1075 1076 //***************************************************************************** 1077 // 1078 // The following are defines for the bit fields in the ADC_O_DCCMP2 register. 1079 // 1080 //***************************************************************************** 1081 #define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 1082 #define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 1083 #define ADC_DCCMP2_COMP1_S 16 1084 #define ADC_DCCMP2_COMP0_S 0 1085 1086 //***************************************************************************** 1087 // 1088 // The following are defines for the bit fields in the ADC_O_DCCMP3 register. 1089 // 1090 //***************************************************************************** 1091 #define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 1092 #define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 1093 #define ADC_DCCMP3_COMP1_S 16 1094 #define ADC_DCCMP3_COMP0_S 0 1095 1096 //***************************************************************************** 1097 // 1098 // The following are defines for the bit fields in the ADC_O_DCCMP4 register. 1099 // 1100 //***************************************************************************** 1101 #define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 1102 #define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 1103 #define ADC_DCCMP4_COMP1_S 16 1104 #define ADC_DCCMP4_COMP0_S 0 1105 1106 //***************************************************************************** 1107 // 1108 // The following are defines for the bit fields in the ADC_O_DCCMP5 register. 1109 // 1110 //***************************************************************************** 1111 #define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 1112 #define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 1113 #define ADC_DCCMP5_COMP1_S 16 1114 #define ADC_DCCMP5_COMP0_S 0 1115 1116 //***************************************************************************** 1117 // 1118 // The following are defines for the bit fields in the ADC_O_DCCMP6 register. 1119 // 1120 //***************************************************************************** 1121 #define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 1122 #define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 1123 #define ADC_DCCMP6_COMP1_S 16 1124 #define ADC_DCCMP6_COMP0_S 0 1125 1126 //***************************************************************************** 1127 // 1128 // The following are defines for the bit fields in the ADC_O_DCCMP7 register. 1129 // 1130 //***************************************************************************** 1131 #define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 1132 #define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 1133 #define ADC_DCCMP7_COMP1_S 16 1134 #define ADC_DCCMP7_COMP0_S 0 1135 1136 //***************************************************************************** 1137 // 1138 // The following are defines for the bit fields in the ADC_O_PP register. 1139 // 1140 //***************************************************************************** 1141 #define ADC_PP_TS 0x00800000 // Temperature Sensor 1142 #define ADC_PP_RSL_M 0x007C0000 // Resolution 1143 #define ADC_PP_TYPE_M 0x00030000 // ADC Architecture 1144 #define ADC_PP_TYPE_SAR 0x00000000 // SAR 1145 #define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count 1146 #define ADC_PP_CH_M 0x000003F0 // ADC Channel Count 1147 #define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate 1148 #define ADC_PP_MSR_125K 0x00000001 // 125 ksps 1149 #define ADC_PP_MSR_250K 0x00000003 // 250 ksps 1150 #define ADC_PP_MSR_500K 0x00000005 // 500 ksps 1151 #define ADC_PP_MSR_1M 0x00000007 // 1 Msps 1152 #define ADC_PP_RSL_S 18 1153 #define ADC_PP_DC_S 10 1154 #define ADC_PP_CH_S 4 1155 1156 //***************************************************************************** 1157 // 1158 // The following are defines for the bit fields in the ADC_O_PC register. 1159 // 1160 //***************************************************************************** 1161 #define ADC_PC_SR_M 0x0000000F // ADC Sample Rate 1162 #define ADC_PC_SR_125K 0x00000001 // 125 ksps 1163 #define ADC_PC_SR_250K 0x00000003 // 250 ksps 1164 #define ADC_PC_SR_500K 0x00000005 // 500 ksps 1165 #define ADC_PC_SR_1M 0x00000007 // 1 Msps 1166 1167 //***************************************************************************** 1168 // 1169 // The following are defines for the bit fields in the ADC_O_CC register. 1170 // 1171 //***************************************************************************** 1172 #define ADC_CC_CS_M 0x0000000F // ADC Clock Source 1173 #define ADC_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the 1174 // PLL bypass is in effect) or the 1175 // 16 MHz clock derived from PLL / 1176 // 25 (default) 1177 #define ADC_CC_CS_PIOSC 0x00000001 // PIOSC 1178 1179 //***************************************************************************** 1180 // 1181 // The following are defines for the the interpretation of the data in the 1182 // SSFIFOx when the ADC TMLB is enabled. 1183 // 1184 //***************************************************************************** 1185 #define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter 1186 #define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator 1187 #define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator 1188 #define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator 1189 #define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator 1190 #define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift 1191 #define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift 1192 1193 //***************************************************************************** 1194 // 1195 // The following definitions are deprecated. 1196 // 1197 //***************************************************************************** 1198 #ifndef DEPRECATED 1199 1200 //***************************************************************************** 1201 // 1202 // The following are deprecated defines for the bit fields in the ADC_O_EMUX 1203 // register. 1204 // 1205 //***************************************************************************** 1206 #define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask 1207 #define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask 1208 #define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask 1209 #define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask 1210 #define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event 1211 #define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event 1212 #define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event 1213 #define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event 1214 1215 //***************************************************************************** 1216 // 1217 // The following are deprecated defines for the bit fields in the ADC_O_SSPRI 1218 // register. 1219 // 1220 //***************************************************************************** 1221 #define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask 1222 #define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask 1223 #define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask 1224 #define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask 1225 1226 //***************************************************************************** 1227 // 1228 // The following are deprecated defines for the ADC sequence register offsets.. 1229 // 1230 //***************************************************************************** 1231 #define ADC_O_SEQ 0x00000040 // Offset to the first sequence 1232 #define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence 1233 #define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register 1234 #define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register 1235 #define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register 1236 #define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register 1237 1238 //***************************************************************************** 1239 // 1240 // The following are deprecated defines for the bit fields in the ADC_SSMUX0, 1241 // ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present 1242 // in all registers.. 1243 // 1244 //***************************************************************************** 1245 #define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask 1246 #define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask 1247 #define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask 1248 #define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask 1249 #define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask 1250 #define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask 1251 #define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask 1252 #define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask 1253 #define ADC_SSMUX_MUX7_SHIFT 28 1254 #define ADC_SSMUX_MUX6_SHIFT 24 1255 #define ADC_SSMUX_MUX5_SHIFT 20 1256 #define ADC_SSMUX_MUX4_SHIFT 16 1257 #define ADC_SSMUX_MUX3_SHIFT 12 1258 #define ADC_SSMUX_MUX2_SHIFT 8 1259 #define ADC_SSMUX_MUX1_SHIFT 4 1260 #define ADC_SSMUX_MUX0_SHIFT 0 1261 1262 //***************************************************************************** 1263 // 1264 // The following are deprecated defines for the bit fields in the ADC_SSCTL0, 1265 // ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present 1266 // in all registers. 1267 // 1268 //***************************************************************************** 1269 #define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select 1270 #define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable 1271 #define ADC_SSCTL_END7 0x20000000 // 8th sequence end select 1272 #define ADC_SSCTL_D7 0x10000000 // 8th differential select 1273 #define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select 1274 #define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable 1275 #define ADC_SSCTL_END6 0x02000000 // 7th sequence end select 1276 #define ADC_SSCTL_D6 0x01000000 // 7th differential select 1277 #define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select 1278 #define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable 1279 #define ADC_SSCTL_END5 0x00200000 // 6th sequence end select 1280 #define ADC_SSCTL_D5 0x00100000 // 6th differential select 1281 #define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select 1282 #define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable 1283 #define ADC_SSCTL_END4 0x00020000 // 5th sequence end select 1284 #define ADC_SSCTL_D4 0x00010000 // 5th differential select 1285 #define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select 1286 #define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable 1287 #define ADC_SSCTL_END3 0x00002000 // 4th sequence end select 1288 #define ADC_SSCTL_D3 0x00001000 // 4th differential select 1289 #define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select 1290 #define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable 1291 #define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select 1292 #define ADC_SSCTL_D2 0x00000100 // 3rd differential select 1293 #define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select 1294 #define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable 1295 #define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select 1296 #define ADC_SSCTL_D1 0x00000010 // 2nd differential select 1297 #define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select 1298 #define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable 1299 #define ADC_SSCTL_END0 0x00000002 // 1st sequence end select 1300 #define ADC_SSCTL_D0 0x00000001 // 1st differential select 1301 1302 //***************************************************************************** 1303 // 1304 // The following are deprecated defines for the bit fields in the ADC_SSFIFO0, 1305 // ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers. 1306 // 1307 //***************************************************************************** 1308 #define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data 1309 #define ADC_SSFIFO_DATA_SHIFT 0 1310 1311 //***************************************************************************** 1312 // 1313 // The following are deprecated defines for the bit fields in the ADC_SSFSTAT0, 1314 // ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. 1315 // 1316 //***************************************************************************** 1317 #define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full 1318 #define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty 1319 #define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer 1320 #define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer 1321 1322 //***************************************************************************** 1323 // 1324 // The following are deprecated defines for the the interpretation of the data 1325 // in the SSFIFOx when the ADC TMLB is enabled. 1326 // 1327 //***************************************************************************** 1328 #define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter 1329 #define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator 1330 #define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator 1331 #define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator 1332 #define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator 1333 #define ADC_TMLB_CNT_S 6 // Sample counter shift 1334 #define ADC_TMLB_MUX_S 0 // Input channel number shift 1335 1336 //***************************************************************************** 1337 // 1338 // The following are deprecated defines for the bit fields in the loopback ADC 1339 // data. 1340 // 1341 //***************************************************************************** 1342 #define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask 1343 #define ADC_LB_CONT 0x00000020 // Continuation sample 1344 #define ADC_LB_DIFF 0x00000010 // Differential sample 1345 #define ADC_LB_TS 0x00000008 // Temperature sensor sample 1346 #define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask 1347 #define ADC_LB_CNT_SHIFT 6 // Sample counter shift 1348 #define ADC_LB_MUX_SHIFT 0 // Input channel number shift 1349 1350 #endif 1351 1352 #endif // __HW_ADC_H__ 1353