1 /****************************************************************************** 2 * Filename: hw_adi_3_refsys_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_ADI_3_REFSYS_H__ 38 #define __HW_ADI_3_REFSYS_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // ADI_3_REFSYS component 44 // 45 //***************************************************************************** 46 // Analog Test Control 47 #define ADI_3_REFSYS_O_SPARE0 0x00000001 48 49 // Internal 50 #define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 51 52 // Internal 53 #define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 54 55 // Internal 56 #define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 57 58 // Internal 59 #define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 60 61 // DCDC Control 0 62 #define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 63 64 // DCDC Control 1 65 #define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 66 67 // DCDC Control 2 68 #define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 69 70 // DCDC Control 3 71 #define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 72 73 // Internal 74 #define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A 75 76 // Internal 77 #define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B 78 79 //***************************************************************************** 80 // 81 // Register: ADI_3_REFSYS_O_SPARE0 82 // 83 //***************************************************************************** 84 // Field: [7:0] SPARE0 85 // 86 // Software should not rely on the value of a reserved. Writing any other value 87 // than the reset value may result in undefined behavior. 88 #define ADI_3_REFSYS_SPARE0_SPARE0_W 8 89 #define ADI_3_REFSYS_SPARE0_SPARE0_M 0x000000FF 90 #define ADI_3_REFSYS_SPARE0_SPARE0_S 0 91 92 //***************************************************************************** 93 // 94 // Register: ADI_3_REFSYS_O_REFSYSCTL0 95 // 96 //***************************************************************************** 97 // Field: [7:0] TESTCTL 98 // 99 // Internal. Only to be used through TI provided API. 100 // ENUMs: 101 // BMCOMPOUT Internal. Only to be used through TI provided API. 102 // VTEMP Internal. Only to be used through TI provided API. 103 // VREF0P8V Internal. Only to be used through TI provided API. 104 // VBGUNBUFF Internal. Only to be used through TI provided API. 105 // VBG Internal. Only to be used through TI provided API. 106 // IREF4U Internal. Only to be used through TI provided API. 107 // IVREF4U Internal. Only to be used through TI provided API. 108 // IPTAT2U Internal. Only to be used through TI provided API. 109 // NC Internal. Only to be used through TI provided API. 110 #define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 111 #define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF 112 #define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 113 #define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 114 #define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 115 #define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 116 #define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 117 #define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 118 #define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 119 #define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 120 #define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 121 #define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 122 123 //***************************************************************************** 124 // 125 // Register: ADI_3_REFSYS_O_REFSYSCTL1 126 // 127 //***************************************************************************** 128 // Field: [7:3] TRIM_VDDS_BOD 129 // 130 // Internal. Only to be used through TI provided API. 131 // ENUMs: 132 // POS_27 Internal. Only to be used through TI provided API. 133 // POS_26 Internal. Only to be used through TI provided API. 134 // POS_25 Internal. Only to be used through TI provided API. 135 // POS_24 Internal. Only to be used through TI provided API. 136 // POS_31 Internal. Only to be used through TI provided API. 137 // POS_30 Internal. Only to be used through TI provided API. 138 // POS_29 Internal. Only to be used through TI provided API. 139 // POS_28 Internal. Only to be used through TI provided API. 140 // POS_19 Internal. Only to be used through TI provided API. 141 // POS_18 Internal. Only to be used through TI provided API. 142 // POS_17 Internal. Only to be used through TI provided API. 143 // POS_16 Internal. Only to be used through TI provided API. 144 // POS_23 Internal. Only to be used through TI provided API. 145 // POS_22 Internal. Only to be used through TI provided API. 146 // POS_21 Internal. Only to be used through TI provided API. 147 // POS_20 Internal. Only to be used through TI provided API. 148 // POS_11 Internal. Only to be used through TI provided API. 149 // POS_10 Internal. Only to be used through TI provided API. 150 // POS_9 Internal. Only to be used through TI provided API. 151 // POS_8 Internal. Only to be used through TI provided API. 152 // POS_15 Internal. Only to be used through TI provided API. 153 // POS_14 Internal. Only to be used through TI provided API. 154 // POS_13 Internal. Only to be used through TI provided API. 155 // POS_12 Internal. Only to be used through TI provided API. 156 // POS_3 Internal. Only to be used through TI provided API. 157 // POS_2 Internal. Only to be used through TI provided API. 158 // POS_1 Internal. Only to be used through TI provided API. 159 // POS_0 Internal. Only to be used through TI provided API. 160 // POS_7 Internal. Only to be used through TI provided API. 161 // POS_6 Internal. Only to be used through TI provided API. 162 // POS_5 Internal. Only to be used through TI provided API. 163 // POS_4 Internal. Only to be used through TI provided API. 164 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 165 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 166 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 167 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 168 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 169 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 170 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 171 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 172 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 173 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 174 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 175 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 176 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 177 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 178 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 179 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 180 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 181 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 182 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 183 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 184 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 185 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 186 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 187 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 188 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 189 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 190 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 191 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 192 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 193 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 194 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 195 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 196 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 197 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 198 #define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 199 200 // Field: [2] BATMON_COMP_TEST_EN 201 // 202 // Internal. Only to be used through TI provided API. 203 // ENUMs: 204 // EN Internal. Only to be used through TI provided API. 205 // DIS Internal. Only to be used through TI provided API. 206 #define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 207 #define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_BITN 2 208 #define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 209 #define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 210 #define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 211 #define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 212 213 // Field: [1:0] TESTCTL 214 // 215 // Internal. Only to be used through TI provided API. 216 // ENUMs: 217 // IPTAT1U Internal. Only to be used through TI provided API. 218 // BMCOMPIN Internal. Only to be used through TI provided API. 219 // NC Internal. Only to be used through TI provided API. 220 #define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 221 #define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 222 #define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 223 #define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 224 #define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 225 #define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 226 227 //***************************************************************************** 228 // 229 // Register: ADI_3_REFSYS_O_REFSYSCTL2 230 // 231 //***************************************************************************** 232 // Field: [7:4] TRIM_VREF 233 // 234 // Internal. Only to be used through TI provided API. 235 #define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 236 #define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 237 #define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 238 239 // Field: [1:0] TRIM_TSENSE 240 // 241 // Internal. Only to be used through TI provided API. 242 #define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 243 #define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 244 #define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 245 246 //***************************************************************************** 247 // 248 // Register: ADI_3_REFSYS_O_REFSYSCTL3 249 // 250 //***************************************************************************** 251 // Field: [7] BOD_BG_TRIM_EN 252 // 253 // Internal. Only to be used through TI provided API. 254 #define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 255 #define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_BITN 7 256 #define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 257 #define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 258 259 // Field: [6] VTEMP_EN 260 // 261 // Internal. Only to be used through TI provided API. 262 // ENUMs: 263 // EN Internal. Only to be used through TI provided API. 264 // DIS Internal. Only to be used through TI provided API. 265 #define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 266 #define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_BITN 6 267 #define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 268 #define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 269 #define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 270 #define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 271 272 // Field: [5:0] TRIM_VBG 273 // 274 // Internal. Only to be used through TI provided API. 275 #define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 276 #define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F 277 #define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 278 279 //***************************************************************************** 280 // 281 // Register: ADI_3_REFSYS_O_DCDCCTL0 282 // 283 //***************************************************************************** 284 // Field: [7:5] GLDO_ISRC 285 // 286 // Set charge and re-charge current level. 287 // 2's complement encoding. 288 // 289 // 0x0: Default 11mA. 290 // 0x3: Max 15mA. 291 // 0x4: Max 5mA 292 #define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 293 #define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 294 #define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 295 296 // Field: [4:0] VDDR_TRIM 297 // 298 // Set the VDDR voltage. 299 // Proprietary encoding. 300 // 301 // Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. 302 // Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. 303 // Step size = 16mV 304 // 305 // 0x00: Default, about 1.63V. 306 // 0x05: Typical voltage after trim voltage 1.71V. 307 // 0x15: Max voltage 1.96V. 308 // 0x16: Min voltage 1.47V. 309 #define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 310 #define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F 311 #define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 312 313 //***************************************************************************** 314 // 315 // Register: ADI_3_REFSYS_O_DCDCCTL1 316 // 317 //***************************************************************************** 318 // Field: [7:6] IPTAT_TRIM 319 // 320 // Trim GLDO bias current. 321 // Proprietary encoding. 322 // 323 // 0x0: Default 324 // 0x1: Increase GLDO bias by 1.3x. 325 // 0x2: Increase GLDO bias by 1.6x. 326 // 0x3: Decrease GLDO bias by 0.7x. 327 #define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 328 #define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 329 #define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 330 331 // Field: [5] VDDR_OK_HYST 332 // 333 // Increase the hysteresis for when VDDR is considered ok. 334 // 335 // 0: Hysteresis = 60mV 336 // 1: Hysteresis = 70mV 337 #define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 338 #define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_BITN 5 339 #define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 340 #define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 341 342 // Field: [4:0] VDDR_TRIM_SLEEP 343 // 344 // Set the min VDDR voltage threshold during sleep mode. 345 // Proprietary encoding. 346 // 347 // Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. 348 // Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. 349 // Step size = 16mV 350 // 351 // 0x00: Default, about 1.63V. 352 // 0x19: Typical voltage after trim voltage 1.52V. 353 // 0x15: Max voltage 1.96V. 354 // 0x16: Min voltage 1.47V. 355 #define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 356 #define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F 357 #define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 358 359 //***************************************************************************** 360 // 361 // Register: ADI_3_REFSYS_O_DCDCCTL2 362 // 363 //***************************************************************************** 364 // Field: [6] TURNON_EA_SW 365 // 366 // Turn on erroramp switch 367 // 368 // 0: Erroramp Off (Default) 369 // 1: Erroramp On. Turns on GLDO error amp switch. 370 #define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 371 #define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_BITN 6 372 #define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 373 #define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 374 375 // Field: [5] TEST_VDDR 376 // 377 // Connect VDDR to ATEST bus 378 // 379 // 0: Not connected. 380 // 1: Connected 381 // 382 // Set TESTSEL = 0x0 first before setting this bit. 383 #define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 384 #define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_BITN 5 385 #define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 386 #define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 387 388 // Field: [4] BIAS_DIS 389 // 390 // Disable dummy bias current. 391 // 392 // 0: Dummy bias current on (Default) 393 // 1: Dummy bias current off 394 #define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 395 #define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_BITN 4 396 #define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 397 #define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 398 399 // Field: [3:0] TESTSEL 400 // 401 // Select signal for test bus, one hot. 402 // ENUMs: 403 // VDDROK VDDR_OK connected to test bus. 404 // IB1U 1uA bias current connected to test bus. 405 // PASSGATE Pass transistor gate voltage connected to test 406 // bus. 407 // ERRAMP_OUT Error amp output voltage connected to test bus. 408 // NC No signal connected to test bus. 409 #define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 410 #define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F 411 #define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 412 #define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 413 #define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 414 #define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 415 #define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 416 #define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 417 418 //***************************************************************************** 419 // 420 // Register: ADI_3_REFSYS_O_DCDCCTL3 421 // 422 //***************************************************************************** 423 //***************************************************************************** 424 // 425 // Register: ADI_3_REFSYS_O_DCDCCTL4 426 // 427 //***************************************************************************** 428 // Field: [7:6] DEADTIME_TRIM 429 // 430 // Internal. Only to be used through TI provided API. 431 #define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 432 #define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 433 #define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 434 435 // Field: [5:3] LOW_EN_SEL 436 // 437 // Internal. Only to be used through TI provided API. 438 #define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 439 #define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 440 #define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 441 442 // Field: [2:0] HIGH_EN_SEL 443 // 444 // Internal. Only to be used through TI provided API. 445 #define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 446 #define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 447 #define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 448 449 //***************************************************************************** 450 // 451 // Register: ADI_3_REFSYS_O_DCDCCTL5 452 // 453 //***************************************************************************** 454 // Field: [5] TESTN 455 // 456 // Internal. Only to be used through TI provided API. 457 #define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 458 #define ADI_3_REFSYS_DCDCCTL5_TESTN_BITN 5 459 #define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 460 #define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 461 462 // Field: [4] TESTP 463 // 464 // Internal. Only to be used through TI provided API. 465 #define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 466 #define ADI_3_REFSYS_DCDCCTL5_TESTP_BITN 4 467 #define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 468 #define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 469 470 // Field: [3] DITHER_EN 471 // 472 // Internal. Only to be used through TI provided API. 473 // ENUMs: 474 // EN Internal. Only to be used through TI provided API. 475 // DIS Internal. Only to be used through TI provided API. 476 #define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 477 #define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_BITN 3 478 #define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 479 #define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 480 #define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 481 #define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 482 483 // Field: [2:0] IPEAK 484 // 485 // Internal. Only to be used through TI provided API. 486 #define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 487 #define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 488 #define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 489 490 491 #endif // __ADI_3_REFSYS__ 492