1 //***************************************************************************** 2 // 3 // hw_can.h - Defines and macros used when accessing the CAN controllers. 4 // 5 // Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_CAN_H__ 41 #define __HW_CAN_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the CAN register offsets. 46 // 47 //***************************************************************************** 48 #define CAN_O_CTL 0x00000000 // CAN Control 49 #define CAN_O_STS 0x00000004 // CAN Status 50 #define CAN_O_ERR 0x00000008 // CAN Error Counter 51 #define CAN_O_BIT 0x0000000C // CAN Bit Timing 52 #define CAN_O_INT 0x00000010 // CAN Interrupt 53 #define CAN_O_TST 0x00000014 // CAN Test 54 #define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler 55 // Extension 56 #define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request 57 #define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask 58 #define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1 59 #define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2 60 #define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1 61 #define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2 62 #define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control 63 #define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1 64 #define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2 65 #define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1 66 #define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2 67 #define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request 68 #define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask 69 #define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1 70 #define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2 71 #define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1 72 #define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2 73 #define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control 74 #define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1 75 #define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2 76 #define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1 77 #define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2 78 #define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1 79 #define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2 80 #define CAN_O_NWDA1 0x00000120 // CAN New Data 1 81 #define CAN_O_NWDA2 0x00000124 // CAN New Data 2 82 #define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending 83 #define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending 84 #define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid 85 #define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid 86 87 //***************************************************************************** 88 // 89 // The following are defines for the bit fields in the CAN_O_CTL register. 90 // 91 //***************************************************************************** 92 #define CAN_CTL_TEST 0x00000080 // Test Mode Enable 93 #define CAN_CTL_CCE 0x00000040 // Configuration Change Enable 94 #define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission 95 #define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable 96 #define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable 97 #define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable 98 #define CAN_CTL_INIT 0x00000001 // Initialization 99 100 //***************************************************************************** 101 // 102 // The following are defines for the bit fields in the CAN_O_STS register. 103 // 104 //***************************************************************************** 105 #define CAN_STS_BOFF 0x00000080 // Bus-Off Status 106 #define CAN_STS_EWARN 0x00000040 // Warning Status 107 #define CAN_STS_EPASS 0x00000020 // Error Passive 108 #define CAN_STS_RXOK 0x00000010 // Received a Message Successfully 109 #define CAN_STS_TXOK 0x00000008 // Transmitted a Message 110 // Successfully 111 #define CAN_STS_LEC_M 0x00000007 // Last Error Code 112 #define CAN_STS_LEC_NONE 0x00000000 // No Error 113 #define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error 114 #define CAN_STS_LEC_FORM 0x00000002 // Format Error 115 #define CAN_STS_LEC_ACK 0x00000003 // ACK Error 116 #define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error 117 #define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error 118 #define CAN_STS_LEC_CRC 0x00000006 // CRC Error 119 #define CAN_STS_LEC_NOEVENT 0x00000007 // No Event 120 121 //***************************************************************************** 122 // 123 // The following are defines for the bit fields in the CAN_O_ERR register. 124 // 125 //***************************************************************************** 126 #define CAN_ERR_RP 0x00008000 // Received Error Passive 127 #define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter 128 #define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter 129 #define CAN_ERR_REC_S 8 130 #define CAN_ERR_TEC_S 0 131 132 //***************************************************************************** 133 // 134 // The following are defines for the bit fields in the CAN_O_BIT register. 135 // 136 //***************************************************************************** 137 #define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point 138 #define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point 139 #define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width 140 #define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler 141 #define CAN_BIT_TSEG2_S 12 142 #define CAN_BIT_TSEG1_S 8 143 #define CAN_BIT_SJW_S 6 144 #define CAN_BIT_BRP_S 0 145 146 //***************************************************************************** 147 // 148 // The following are defines for the bit fields in the CAN_O_INT register. 149 // 150 //***************************************************************************** 151 #define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier 152 #define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending 153 #define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt 154 155 //***************************************************************************** 156 // 157 // The following are defines for the bit fields in the CAN_O_TST register. 158 // 159 //***************************************************************************** 160 #define CAN_TST_RX 0x00000080 // Receive Observation 161 #define CAN_TST_TX_M 0x00000060 // Transmit Control 162 #define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control 163 #define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point 164 #define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low 165 #define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High 166 #define CAN_TST_LBACK 0x00000010 // Loopback Mode 167 #define CAN_TST_SILENT 0x00000008 // Silent Mode 168 #define CAN_TST_BASIC 0x00000004 // Basic Mode 169 170 //***************************************************************************** 171 // 172 // The following are defines for the bit fields in the CAN_O_BRPE register. 173 // 174 //***************************************************************************** 175 #define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension 176 #define CAN_BRPE_BRPE_S 0 177 178 //***************************************************************************** 179 // 180 // The following are defines for the bit fields in the CAN_O_IF1CRQ register. 181 // 182 //***************************************************************************** 183 #define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag 184 #define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number 185 #define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number; 186 // it is interpreted as 0x20, or 187 // object 32 188 #define CAN_IF1CRQ_MNUM_S 0 189 190 //***************************************************************************** 191 // 192 // The following are defines for the bit fields in the CAN_O_IF1CMSK register. 193 // 194 //***************************************************************************** 195 #define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read 196 #define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits 197 #define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits 198 #define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits 199 #define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit 200 #define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data 201 #define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request 202 #define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 203 #define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 204 205 //***************************************************************************** 206 // 207 // The following are defines for the bit fields in the CAN_O_IF1MSK1 register. 208 // 209 //***************************************************************************** 210 #define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask 211 #define CAN_IF1MSK1_IDMSK_S 0 212 213 //***************************************************************************** 214 // 215 // The following are defines for the bit fields in the CAN_O_IF1MSK2 register. 216 // 217 //***************************************************************************** 218 #define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier 219 #define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction 220 #define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask 221 #define CAN_IF1MSK2_IDMSK_S 0 222 223 //***************************************************************************** 224 // 225 // The following are defines for the bit fields in the CAN_O_IF1ARB1 register. 226 // 227 //***************************************************************************** 228 #define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier 229 #define CAN_IF1ARB1_ID_S 0 230 231 //***************************************************************************** 232 // 233 // The following are defines for the bit fields in the CAN_O_IF1ARB2 register. 234 // 235 //***************************************************************************** 236 #define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid 237 #define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier 238 #define CAN_IF1ARB2_DIR 0x00002000 // Message Direction 239 #define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier 240 #define CAN_IF1ARB2_ID_S 0 241 242 //***************************************************************************** 243 // 244 // The following are defines for the bit fields in the CAN_O_IF1MCTL register. 245 // 246 //***************************************************************************** 247 #define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data 248 #define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost 249 #define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending 250 #define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask 251 #define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable 252 #define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable 253 #define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable 254 #define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request 255 #define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer 256 #define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code 257 #define CAN_IF1MCTL_DLC_S 0 258 259 //***************************************************************************** 260 // 261 // The following are defines for the bit fields in the CAN_O_IF1DA1 register. 262 // 263 //***************************************************************************** 264 #define CAN_IF1DA1_DATA_M 0x0000FFFF // Data 265 #define CAN_IF1DA1_DATA_S 0 266 267 //***************************************************************************** 268 // 269 // The following are defines for the bit fields in the CAN_O_IF1DA2 register. 270 // 271 //***************************************************************************** 272 #define CAN_IF1DA2_DATA_M 0x0000FFFF // Data 273 #define CAN_IF1DA2_DATA_S 0 274 275 //***************************************************************************** 276 // 277 // The following are defines for the bit fields in the CAN_O_IF1DB1 register. 278 // 279 //***************************************************************************** 280 #define CAN_IF1DB1_DATA_M 0x0000FFFF // Data 281 #define CAN_IF1DB1_DATA_S 0 282 283 //***************************************************************************** 284 // 285 // The following are defines for the bit fields in the CAN_O_IF1DB2 register. 286 // 287 //***************************************************************************** 288 #define CAN_IF1DB2_DATA_M 0x0000FFFF // Data 289 #define CAN_IF1DB2_DATA_S 0 290 291 //***************************************************************************** 292 // 293 // The following are defines for the bit fields in the CAN_O_IF2CRQ register. 294 // 295 //***************************************************************************** 296 #define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag 297 #define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number 298 #define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number; 299 // it is interpreted as 0x20, or 300 // object 32 301 #define CAN_IF2CRQ_MNUM_S 0 302 303 //***************************************************************************** 304 // 305 // The following are defines for the bit fields in the CAN_O_IF2CMSK register. 306 // 307 //***************************************************************************** 308 #define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read 309 #define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits 310 #define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits 311 #define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits 312 #define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit 313 #define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data 314 #define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request 315 #define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 316 #define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 317 318 //***************************************************************************** 319 // 320 // The following are defines for the bit fields in the CAN_O_IF2MSK1 register. 321 // 322 //***************************************************************************** 323 #define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask 324 #define CAN_IF2MSK1_IDMSK_S 0 325 326 //***************************************************************************** 327 // 328 // The following are defines for the bit fields in the CAN_O_IF2MSK2 register. 329 // 330 //***************************************************************************** 331 #define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier 332 #define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction 333 #define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask 334 #define CAN_IF2MSK2_IDMSK_S 0 335 336 //***************************************************************************** 337 // 338 // The following are defines for the bit fields in the CAN_O_IF2ARB1 register. 339 // 340 //***************************************************************************** 341 #define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier 342 #define CAN_IF2ARB1_ID_S 0 343 344 //***************************************************************************** 345 // 346 // The following are defines for the bit fields in the CAN_O_IF2ARB2 register. 347 // 348 //***************************************************************************** 349 #define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid 350 #define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier 351 #define CAN_IF2ARB2_DIR 0x00002000 // Message Direction 352 #define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier 353 #define CAN_IF2ARB2_ID_S 0 354 355 //***************************************************************************** 356 // 357 // The following are defines for the bit fields in the CAN_O_IF2MCTL register. 358 // 359 //***************************************************************************** 360 #define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data 361 #define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost 362 #define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending 363 #define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask 364 #define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable 365 #define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable 366 #define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable 367 #define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request 368 #define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer 369 #define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code 370 #define CAN_IF2MCTL_DLC_S 0 371 372 //***************************************************************************** 373 // 374 // The following are defines for the bit fields in the CAN_O_IF2DA1 register. 375 // 376 //***************************************************************************** 377 #define CAN_IF2DA1_DATA_M 0x0000FFFF // Data 378 #define CAN_IF2DA1_DATA_S 0 379 380 //***************************************************************************** 381 // 382 // The following are defines for the bit fields in the CAN_O_IF2DA2 register. 383 // 384 //***************************************************************************** 385 #define CAN_IF2DA2_DATA_M 0x0000FFFF // Data 386 #define CAN_IF2DA2_DATA_S 0 387 388 //***************************************************************************** 389 // 390 // The following are defines for the bit fields in the CAN_O_IF2DB1 register. 391 // 392 //***************************************************************************** 393 #define CAN_IF2DB1_DATA_M 0x0000FFFF // Data 394 #define CAN_IF2DB1_DATA_S 0 395 396 //***************************************************************************** 397 // 398 // The following are defines for the bit fields in the CAN_O_IF2DB2 register. 399 // 400 //***************************************************************************** 401 #define CAN_IF2DB2_DATA_M 0x0000FFFF // Data 402 #define CAN_IF2DB2_DATA_S 0 403 404 //***************************************************************************** 405 // 406 // The following are defines for the bit fields in the CAN_O_TXRQ1 register. 407 // 408 //***************************************************************************** 409 #define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits 410 #define CAN_TXRQ1_TXRQST_S 0 411 412 //***************************************************************************** 413 // 414 // The following are defines for the bit fields in the CAN_O_TXRQ2 register. 415 // 416 //***************************************************************************** 417 #define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits 418 #define CAN_TXRQ2_TXRQST_S 0 419 420 //***************************************************************************** 421 // 422 // The following are defines for the bit fields in the CAN_O_NWDA1 register. 423 // 424 //***************************************************************************** 425 #define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits 426 #define CAN_NWDA1_NEWDAT_S 0 427 428 //***************************************************************************** 429 // 430 // The following are defines for the bit fields in the CAN_O_NWDA2 register. 431 // 432 //***************************************************************************** 433 #define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits 434 #define CAN_NWDA2_NEWDAT_S 0 435 436 //***************************************************************************** 437 // 438 // The following are defines for the bit fields in the CAN_O_MSG1INT register. 439 // 440 //***************************************************************************** 441 #define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits 442 #define CAN_MSG1INT_INTPND_S 0 443 444 //***************************************************************************** 445 // 446 // The following are defines for the bit fields in the CAN_O_MSG2INT register. 447 // 448 //***************************************************************************** 449 #define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits 450 #define CAN_MSG2INT_INTPND_S 0 451 452 //***************************************************************************** 453 // 454 // The following are defines for the bit fields in the CAN_O_MSG1VAL register. 455 // 456 //***************************************************************************** 457 #define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits 458 #define CAN_MSG1VAL_MSGVAL_S 0 459 460 //***************************************************************************** 461 // 462 // The following are defines for the bit fields in the CAN_O_MSG2VAL register. 463 // 464 //***************************************************************************** 465 #define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits 466 #define CAN_MSG2VAL_MSGVAL_S 0 467 468 //***************************************************************************** 469 // 470 // The following definitions are deprecated. 471 // 472 //***************************************************************************** 473 #ifndef DEPRECATED 474 475 //***************************************************************************** 476 // 477 // The following are deprecated defines for the CAN register offsets. 478 // 479 //***************************************************************************** 480 #define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg 481 #define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg 482 #define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg 483 #define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg 484 485 //***************************************************************************** 486 // 487 // The following are deprecated defines for the bit fields in the CAN_O_STS 488 // register. 489 // 490 //***************************************************************************** 491 #define CAN_STS_LEC_MSK 0x00000007 // Last Error Code 492 493 //***************************************************************************** 494 // 495 // The following are deprecated defines for the bit fields in the CAN_O_ERR 496 // register. 497 // 498 //***************************************************************************** 499 #define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status 500 #define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status 501 #define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos 502 #define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos 503 504 //***************************************************************************** 505 // 506 // The following are deprecated defines for the bit fields in the CAN_O_BIT 507 // register. 508 // 509 //***************************************************************************** 510 #define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point 511 #define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point 512 #define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width 513 #define CAN_BIT_BRP 0x0000003F // Baud rate prescaler 514 515 //***************************************************************************** 516 // 517 // The following are deprecated defines for the bit fields in the CAN_O_INT 518 // register. 519 // 520 //***************************************************************************** 521 #define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier 522 523 //***************************************************************************** 524 // 525 // The following are deprecated defines for the bit fields in the CAN_O_TST 526 // register. 527 // 528 //***************************************************************************** 529 #define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin 530 531 //***************************************************************************** 532 // 533 // The following are deprecated defines for the bit fields in the CAN_O_BRPE 534 // register. 535 // 536 //***************************************************************************** 537 #define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension 538 539 //***************************************************************************** 540 // 541 // The following are deprecated defines for the bit fields in the CAN_O_TXRQ1 542 // register. 543 // 544 //***************************************************************************** 545 #define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits 546 547 //***************************************************************************** 548 // 549 // The following are deprecated defines for the bit fields in the CAN_O_TXRQ2 550 // register. 551 // 552 //***************************************************************************** 553 #define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits 554 555 //***************************************************************************** 556 // 557 // The following are deprecated defines for the bit fields in the CAN_O_NWDA1 558 // register. 559 // 560 //***************************************************************************** 561 #define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits 562 563 //***************************************************************************** 564 // 565 // The following are deprecated defines for the bit fields in the CAN_O_NWDA2 566 // register. 567 // 568 //***************************************************************************** 569 #define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits 570 571 //***************************************************************************** 572 // 573 // The following are deprecated defines for the bit fields in the CAN_O_MSGINT1 574 // register. 575 // 576 //***************************************************************************** 577 #define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits 578 579 //***************************************************************************** 580 // 581 // The following are deprecated defines for the bit fields in the CAN_O_MSGINT2 582 // register. 583 // 584 //***************************************************************************** 585 #define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits 586 587 //***************************************************************************** 588 // 589 // The following are deprecated defines for the bit fields in the CAN_O_MSGVAL1 590 // register. 591 // 592 //***************************************************************************** 593 #define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits 594 595 //***************************************************************************** 596 // 597 // The following are deprecated defines for the bit fields in the CAN_O_MSGVAL2 598 // register. 599 // 600 //***************************************************************************** 601 #define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits 602 603 //***************************************************************************** 604 // 605 // The following are deprecated defines for the reset values of the can 606 // registers. 607 // 608 //***************************************************************************** 609 #define CAN_RV_IF1MSK2 0x0000FFFF 610 #define CAN_RV_IF1MSK1 0x0000FFFF 611 #define CAN_RV_IF2MSK1 0x0000FFFF 612 #define CAN_RV_IF2MSK2 0x0000FFFF 613 #define CAN_RV_BIT 0x00002301 614 #define CAN_RV_CTL 0x00000001 615 #define CAN_RV_IF1CRQ 0x00000001 616 #define CAN_RV_IF2CRQ 0x00000001 617 #define CAN_RV_TXRQ2 0x00000000 618 #define CAN_RV_IF2DB1 0x00000000 619 #define CAN_RV_INT 0x00000000 620 #define CAN_RV_IF1DB2 0x00000000 621 #define CAN_RV_BRPE 0x00000000 622 #define CAN_RV_IF2DA2 0x00000000 623 #define CAN_RV_MSGVAL2 0x00000000 624 #define CAN_RV_TXRQ1 0x00000000 625 #define CAN_RV_IF1MCTL 0x00000000 626 #define CAN_RV_IF1DB1 0x00000000 627 #define CAN_RV_STS 0x00000000 628 #define CAN_RV_MSGINT1 0x00000000 629 #define CAN_RV_IF1DA2 0x00000000 630 #define CAN_RV_TST 0x00000000 631 #define CAN_RV_IF1ARB1 0x00000000 632 #define CAN_RV_IF1ARB2 0x00000000 633 #define CAN_RV_NWDA2 0x00000000 634 #define CAN_RV_IF2CMSK 0x00000000 635 #define CAN_RV_NWDA1 0x00000000 636 #define CAN_RV_IF1DA1 0x00000000 637 #define CAN_RV_IF2DA1 0x00000000 638 #define CAN_RV_IF2MCTL 0x00000000 639 #define CAN_RV_MSGVAL1 0x00000000 640 #define CAN_RV_IF1CMSK 0x00000000 641 #define CAN_RV_ERR 0x00000000 642 #define CAN_RV_IF2ARB2 0x00000000 643 #define CAN_RV_MSGINT2 0x00000000 644 #define CAN_RV_IF2ARB1 0x00000000 645 #define CAN_RV_IF2DB2 0x00000000 646 647 //***************************************************************************** 648 // 649 // The following are deprecated defines for the bit fields in the CAN_IF1CRQ 650 // and CAN_IF1CRQ registers. 651 // Note: All bits may not be available in all registers. 652 // 653 //***************************************************************************** 654 #define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status 655 #define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number 656 657 //***************************************************************************** 658 // 659 // The following are deprecated defines for the bit fields in the CAN_IF1CMSK 660 // and CAN_IF2CMSK registers. 661 // Note: All bits may not be available in all registers. 662 // 663 //***************************************************************************** 664 #define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read 665 #define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits 666 #define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits 667 #define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits 668 #define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit 669 #define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1) 670 #define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0) 671 #define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3 672 #define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7 673 674 //***************************************************************************** 675 // 676 // The following are deprecated defines for the bit fields in the CAN_IF1MSK1 677 // and CAN_IF2MSK1 registers. 678 // Note: All bits may not be available in all registers. 679 // 680 //***************************************************************************** 681 #define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask 682 683 //***************************************************************************** 684 // 685 // The following are deprecated defines for the bit fields in the CAN_IF1MSK2 686 // and CAN_IF2MSK2 registers. 687 // Note: All bits may not be available in all registers. 688 // 689 //***************************************************************************** 690 #define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier 691 #define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction 692 #define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier 693 694 //***************************************************************************** 695 // 696 // The following are deprecated defines for the bit fields in the CAN_IF1ARB1 697 // and CAN_IF2ARB1 registers. 698 // Note: All bits may not be available in all registers. 699 // 700 //***************************************************************************** 701 #define CAN_IFARB1_ID 0x0000FFFF // Identifier 702 703 //***************************************************************************** 704 // 705 // The following are deprecated defines for the bit fields in the CAN_IF1ARB2 706 // and CAN_IF2ARB2 registers. 707 // Note: All bits may not be available in all registers. 708 // 709 //***************************************************************************** 710 #define CAN_IFARB2_MSGVAL 0x00008000 // Message valid 711 #define CAN_IFARB2_XTD 0x00004000 // Extended identifier 712 #define CAN_IFARB2_DIR 0x00002000 // Message direction 713 #define CAN_IFARB2_ID 0x00001FFF // Message identifier 714 715 //***************************************************************************** 716 // 717 // The following are deprecated defines for the bit fields in the CAN_IF1MCTL 718 // and CAN_IF2MCTL registers. 719 // Note: All bits may not be available in all registers. 720 // 721 //***************************************************************************** 722 #define CAN_IFMCTL_NEWDAT 0x00008000 // New Data 723 #define CAN_IFMCTL_MSGLST 0x00004000 // Message lost 724 #define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending 725 #define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask 726 #define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable 727 #define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable 728 #define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable 729 #define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request 730 #define CAN_IFMCTL_EOB 0x00000080 // End of buffer 731 #define CAN_IFMCTL_DLC 0x0000000F // Data length code 732 733 //***************************************************************************** 734 // 735 // The following are deprecated defines for the bit fields in the CAN_IF1DA1 736 // and CAN_IF2DA1 registers. 737 // Note: All bits may not be available in all registers. 738 // 739 //***************************************************************************** 740 #define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0 741 742 //***************************************************************************** 743 // 744 // The following are deprecated defines for the bit fields in the CAN_IF1DA2 745 // and CAN_IF2DA2 registers. 746 // Note: All bits may not be available in all registers. 747 // 748 //***************************************************************************** 749 #define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2 750 751 //***************************************************************************** 752 // 753 // The following are deprecated defines for the bit fields in the CAN_IF1DB1 754 // and CAN_IF2DB1 registers. 755 // Note: All bits may not be available in all registers. 756 // 757 //***************************************************************************** 758 #define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4 759 760 //***************************************************************************** 761 // 762 // The following are deprecated defines for the bit fields in the CAN_IF1DB2 763 // and CAN_IF2DB2 registers. 764 // Note: All bits may not be available in all registers. 765 // 766 //***************************************************************************** 767 #define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6 768 769 #endif 770 771 #endif // __HW_CAN_H__ 772