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Searched refs:CCR (Results 1 – 25 of 61) sorted by relevance

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/external/platform/stm32f0xx/STM32F0xx_HAL_Driver/
A Dstm32f0xx_hal_dma.c178 tmp = hdma->Instance->CCR; in HAL_DMA_Init()
192 hdma->Instance->CCR = tmp; in HAL_DMA_Init()
234 hdma->Instance->CCR &= ~DMA_CCR_EN; in HAL_DMA_DeInit()
237 hdma->Instance->CCR = 0U; in HAL_DMA_DeInit()
322 hdma->Instance->CCR |= DMA_CCR_EN; in HAL_DMA_Start()
363 hdma->Instance->CCR &= ~DMA_CCR_EN; in HAL_DMA_Start_IT()
377 hdma->Instance->CCR &= ~DMA_IT_HT; in HAL_DMA_Start_IT()
381 hdma->Instance->CCR |= DMA_CCR_EN; in HAL_DMA_Start_IT()
407 hdma->Instance->CCR &= ~DMA_CCR_EN; in HAL_DMA_Abort()
445 hdma->Instance->CCR &= ~DMA_CCR_EN; in HAL_DMA_Abort_IT()
[all …]
A Dstm32f0xx_ll_dma.c214 CLEAR_BIT(tmp->CCR, DMA_CCR_EN); in LL_DMA_DeInit()
217 LL_DMA_WriteReg(tmp, CCR, 0U); in LL_DMA_DeInit()
A Dstm32f0xx_hal_adc.c667 ADC->CCR &= ~(ADC_CCR_ALL); in HAL_ADC_DeInit()
1676 ADC->CCR |= ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); in HAL_ADC_ConfigChannel()
1705 ADC->CCR &= ~ADC_CHANNEL_INTERNAL_PATH(sConfig->Channel); in HAL_ADC_ConfigChannel()
A Dstm32f0xx_hal_i2s.c1213 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) in I2S_DMATxCplt()
1247 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) in I2S_DMARxCplt()
A Dstm32f0xx_hal_irda.c1992 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) in IRDA_DMATransmitCplt()
2035 if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) in IRDA_DMAReceiveCplt()
/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Src/
A Dstm32f7xx_hal_adc_ex.c465 ADC->CCR |= ADC_CCR_DDS; in HAL_ADCEx_MultiModeStart_DMA()
468 ADC->CCR &= ~ADC_CCR_DDS; in HAL_ADCEx_MultiModeStart_DMA()
531 ADC->CCR &= ~ADC_CCR_DDS; in HAL_ADCEx_MultiModeStop_DMA()
682 ADC->CCR |= ADC_CCR_VBATE; in HAL_ADCEx_InjectedConfigChannel()
688 ADC->CCR |= ADC_CCR_TSVREFE; in HAL_ADCEx_InjectedConfigChannel()
717 ADC->CCR &= ~(ADC_CCR_MULTI); in HAL_ADCEx_MultiModeConfigChannel()
718 ADC->CCR |= multimode->Mode; in HAL_ADCEx_MultiModeConfigChannel()
721 ADC->CCR &= ~(ADC_CCR_DMA); in HAL_ADCEx_MultiModeConfigChannel()
722 ADC->CCR |= multimode->DMAAccessMode; in HAL_ADCEx_MultiModeConfigChannel()
725 ADC->CCR &= ~(ADC_CCR_DELAY); in HAL_ADCEx_MultiModeConfigChannel()
[all …]
A Dstm32f7xx_hal_qspi.c725 … MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit()
799 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive()
872 … MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_IT()
920 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_IT()
970 … MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_DMA()
1052 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_DMA()
1708 … WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
1720 … WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
1729 … WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
1741 … WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
[all …]
A Dstm32f7xx_hal_adc.c435 if (HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) { in HAL_ADC_Start()
639 if (HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) { in HAL_ADC_Start_IT()
1046 ADC->CCR |= ADC_CCR_VBATE; in HAL_ADC_ConfigChannel()
1052 ADC->CCR |= ADC_CCR_TSVREFE; in HAL_ADC_ConfigChannel()
1200 ADC->CCR &= ~(ADC_CCR_ADCPRE); in ADC_Init()
1201 ADC->CCR |= hadc->Init.ClockPrescaler; in ADC_Init()
/external/platform/stm32f1xx/STM32F10x_StdPeriph_Driver/src/
A Dstm32f10x_dma.c113 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); in DMA_DeInit()
116 DMAy_Channelx->CCR = 0; in DMA_DeInit()
219 tmpreg = DMAy_Channelx->CCR; in DMA_Init()
237 DMAy_Channelx->CCR = tmpreg; in DMA_Init()
302 DMAy_Channelx->CCR |= DMA_CCR1_EN; in DMA_Cmd()
307 DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); in DMA_Cmd()
334 DMAy_Channelx->CCR |= DMA_IT; in DMA_ITConfig()
339 DMAy_Channelx->CCR &= ~DMA_IT; in DMA_ITConfig()
A Dstm32f10x_i2c.c271 I2Cx->CCR = tmpreg; in I2C_Init()
852 I2Cx->CCR &= I2C_DutyCycle_2; in I2C_FastModeDutyCycleConfig()
857 I2Cx->CCR |= I2C_DutyCycle_16_9; in I2C_FastModeDutyCycleConfig()
/external/platform/stm32f0xx/STM32F0xx_HAL_Driver/inc/
A Dstm32f0xx_ll_dma.h639 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_IsEnabledChannel()
674 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_ConfigTransfer()
700 …_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_SetDataTransferDirection()
724 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetDataTransferDirection()
771 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMode()
816 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetPeriphIncMode()
861 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMemoryIncMode()
908 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetPeriphSize()
955 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetMemorySize()
1004 …_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, in LL_DMA_GetChannelPriorityLevel()
[all …]
A Dstm32f0xx_hal_dma.h376 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
383 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
398 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRU…
410 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERR…
422 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTE…
A Dstm32f0xx_ll_adc.h1481 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); in LL_ADC_SetCommonPathInternalCh()
1483 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal); in LL_ADC_SetCommonPathInternalCh()
1509 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); in LL_ADC_GetCommonPathInternalCh()
1511 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN)); in LL_ADC_GetCommonPathInternalCh()
/external/arch/arm/arm-m/CMSIS/Include/
A Dcachel1_armv7.h60 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
148 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
A Dcore_cm0.h348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
A Dcore_cm1.h348 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
A Dcore_sc000.h359 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
A Dcore_cm0plus.h366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member
/external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/src/
A Dstm32f2xx_adc.c350 tmpreg1 = ADC->CCR; in ADC_CommonInit()
367 ADC->CCR = tmpreg1; in ADC_CommonInit()
598 ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; in ADC_TempSensorVrefintCmd()
603 ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); in ADC_TempSensorVrefintCmd()
620 ADC->CCR |= (uint32_t)ADC_CCR_VBATE; in ADC_VBATCmd()
625 ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); in ADC_VBATCmd()
1112 ADC->CCR |= (uint32_t)ADC_CCR_DDS; in ADC_MultiModeDMARequestAfterLastTransferCmd()
1117 ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); in ADC_MultiModeDMARequestAfterLastTransferCmd()
A Dstm32f2xx_i2c.c264 I2Cx->CCR = tmpreg; in I2C_Init()
575 I2Cx->CCR &= I2C_DutyCycle_2; in I2C_FastModeDutyCycleConfig()
580 I2Cx->CCR |= I2C_DutyCycle_16_9; in I2C_FastModeDutyCycleConfig()
/external/platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/src/
A Dstm32f4xx_adc.c344 tmpreg1 = ADC->CCR; in ADC_CommonInit()
361 ADC->CCR = tmpreg1; in ADC_CommonInit()
589 ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; in ADC_TempSensorVrefintCmd()
594 ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); in ADC_TempSensorVrefintCmd()
615 ADC->CCR |= (uint32_t)ADC_CCR_VBATE; in ADC_VBATCmd()
620 ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); in ADC_VBATCmd()
1103 ADC->CCR |= (uint32_t)ADC_CCR_DDS; in ADC_MultiModeDMARequestAfterLastTransferCmd()
1108 ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); in ADC_MultiModeDMARequestAfterLastTransferCmd()
A Dstm32f4xx_qspi.c278 tmpreg = QUADSPI->CCR; in QSPI_ComConfig_Init()
295 QUADSPI->CCR = tmpreg; in QSPI_ComConfig_Init()
749 return (QUADSPI->CCR & QUADSPI_CCR_FMODE); in QSPI_GetFMode()
A Dstm32f4xx_i2c.c256 I2Cx->CCR = tmpreg; in I2C_Init()
629 I2Cx->CCR &= I2C_DutyCycle_2; in I2C_FastModeDutyCycleConfig()
634 I2Cx->CCR |= I2C_DutyCycle_16_9; in I2C_FastModeDutyCycleConfig()
A Dstm32f4xx_dsi.c190 DSIx->CCR &= ~DSI_CCR_TXECKDIV; in DSI_Init()
191 DSIx->CCR = DSI_InitStruct->TXEscapeCkdiv; in DSI_Init()
575 DSIx->CCR &= ~DSI_CCR_TOCKDIV; in DSI_ConfigHostTimeouts()
576 DSIx->CCR = ((HostTimeouts->TimeoutCkdiv)<<8); in DSI_ConfigHostTimeouts()
/external/platform/pico/rp2_common/cmsis/stub/CMSIS/Core/Include/
A Dcore_cm0plus.h366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ member

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