1 /****************************************************************************** 2 * Filename: hw_crypto_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_CRYPTO_H__ 38 #define __HW_CRYPTO_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // CRYPTO component 44 // 45 //***************************************************************************** 46 // DMA Channel 0 Control 47 #define CRYPTO_O_DMACH0CTL 0x00000000 48 49 // DMA Channel 0 External Address 50 #define CRYPTO_O_DMACH0EXTADDR 0x00000004 51 52 // DMA Channel 0 Length 53 #define CRYPTO_O_DMACH0LEN 0x0000000C 54 55 // DMA Controller Status 56 #define CRYPTO_O_DMASTAT 0x00000018 57 58 // DMA Controller Software Reset 59 #define CRYPTO_O_DMASWRESET 0x0000001C 60 61 // DMA Channel 1 Control 62 #define CRYPTO_O_DMACH1CTL 0x00000020 63 64 // DMA Channel 1 External Address 65 #define CRYPTO_O_DMACH1EXTADDR 0x00000024 66 67 // DMA Channel 1 Length 68 #define CRYPTO_O_DMACH1LEN 0x0000002C 69 70 // DMA Controller Master Configuration 71 #define CRYPTO_O_DMABUSCFG 0x00000078 72 73 // DMA Controller Port Error 74 #define CRYPTO_O_DMAPORTERR 0x0000007C 75 76 // DMA Controller Version 77 #define CRYPTO_O_DMAHWVER 0x000000FC 78 79 // Key Write Area 80 #define CRYPTO_O_KEYWRITEAREA 0x00000400 81 82 // Key Written Area Status 83 #define CRYPTO_O_KEYWRITTENAREA 0x00000404 84 85 // Key Size 86 #define CRYPTO_O_KEYSIZE 0x00000408 87 88 // Key Read Area 89 #define CRYPTO_O_KEYREADAREA 0x0000040C 90 91 // Clear AES_KEY2/GHASH Key 92 #define CRYPTO_O_AESKEY20 0x00000500 93 94 // Clear AES_KEY2/GHASH Key 95 #define CRYPTO_O_AESKEY21 0x00000504 96 97 // Clear AES_KEY2/GHASH Key 98 #define CRYPTO_O_AESKEY22 0x00000508 99 100 // Clear AES_KEY2/GHASH Key 101 #define CRYPTO_O_AESKEY23 0x0000050C 102 103 // Clear AES_KEY3 104 #define CRYPTO_O_AESKEY30 0x00000510 105 106 // Clear AES_KEY3 107 #define CRYPTO_O_AESKEY31 0x00000514 108 109 // Clear AES_KEY3 110 #define CRYPTO_O_AESKEY32 0x00000518 111 112 // Clear AES_KEY3 113 #define CRYPTO_O_AESKEY33 0x0000051C 114 115 // AES Initialization Vector 116 #define CRYPTO_O_AESIV0 0x00000540 117 118 // AES Initialization Vector 119 #define CRYPTO_O_AESIV1 0x00000544 120 121 // AES Initialization Vector 122 #define CRYPTO_O_AESIV2 0x00000548 123 124 // AES Initialization Vector 125 #define CRYPTO_O_AESIV3 0x0000054C 126 127 // AES Input/Output Buffer Control 128 #define CRYPTO_O_AESCTL 0x00000550 129 130 // Crypto Data Length LSW 131 #define CRYPTO_O_AESDATALEN0 0x00000554 132 133 // Crypto Data Length MSW 134 #define CRYPTO_O_AESDATALEN1 0x00000558 135 136 // AES Authentication Length 137 #define CRYPTO_O_AESAUTHLEN 0x0000055C 138 139 // Data Input/Output 140 #define CRYPTO_O_AESDATAOUT0 0x00000560 141 142 // AES Data Input/Output 0 143 #define CRYPTO_O_AESDATAIN0 0x00000560 144 145 // AES Data Input/Output 3 146 #define CRYPTO_O_AESDATAOUT1 0x00000564 147 148 // AES Data Input/Output 1 149 #define CRYPTO_O_AESDATAIN1 0x00000564 150 151 // AES Data Input/Output 2 152 #define CRYPTO_O_AESDATAOUT2 0x00000568 153 154 // AES Data Input/Output 2 155 #define CRYPTO_O_AESDATAIN2 0x00000568 156 157 // AES Data Input/Output 3 158 #define CRYPTO_O_AESDATAOUT3 0x0000056C 159 160 // Data Input/Output 161 #define CRYPTO_O_AESDATAIN3 0x0000056C 162 163 // AES Tag Output 164 #define CRYPTO_O_AESTAGOUT0 0x00000570 165 166 // AES Tag Output 167 #define CRYPTO_O_AESTAGOUT1 0x00000574 168 169 // AES Tag Output 170 #define CRYPTO_O_AESTAGOUT2 0x00000578 171 172 // AES Tag Output 173 #define CRYPTO_O_AESTAGOUT3 0x0000057C 174 175 // Master Algorithm Select 176 #define CRYPTO_O_ALGSEL 0x00000700 177 178 // Master Protection Control 179 #define CRYPTO_O_DMAPROTCTL 0x00000704 180 181 // Software Reset 182 #define CRYPTO_O_SWRESET 0x00000740 183 184 // Interrupt Configuration 185 #define CRYPTO_O_IRQTYPE 0x00000780 186 187 // Interrupt Enable 188 #define CRYPTO_O_IRQEN 0x00000784 189 190 // Interrupt Clear 191 #define CRYPTO_O_IRQCLR 0x00000788 192 193 // Interrupt Set 194 #define CRYPTO_O_IRQSET 0x0000078C 195 196 // Interrupt Status 197 #define CRYPTO_O_IRQSTAT 0x00000790 198 199 // CTRL Module Version 200 #define CRYPTO_O_HWVER 0x000007FC 201 202 //***************************************************************************** 203 // 204 // Register: CRYPTO_O_DMACH0CTL 205 // 206 //***************************************************************************** 207 // Field: [1] PRIO 208 // 209 // Channel priority: 210 // 211 // A channel with high priority will be served before a channel with low 212 // priority in cases with simultaneous access requests. If both channels have 213 // the same priority access of the channels to the external port is arbitrated 214 // using a Round Robin scheme. 215 // ENUMs: 216 // HIGH Priority high 217 // LOW Priority low 218 #define CRYPTO_DMACH0CTL_PRIO 0x00000002 219 #define CRYPTO_DMACH0CTL_PRIO_BITN 1 220 #define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 221 #define CRYPTO_DMACH0CTL_PRIO_S 1 222 #define CRYPTO_DMACH0CTL_PRIO_HIGH 0x00000002 223 #define CRYPTO_DMACH0CTL_PRIO_LOW 0x00000000 224 225 // Field: [0] EN 226 // 227 // DMA Channel 0 Control 228 // ENUMs: 229 // EN Channel enabled 230 // DIS Channel disabled 231 #define CRYPTO_DMACH0CTL_EN 0x00000001 232 #define CRYPTO_DMACH0CTL_EN_BITN 0 233 #define CRYPTO_DMACH0CTL_EN_M 0x00000001 234 #define CRYPTO_DMACH0CTL_EN_S 0 235 #define CRYPTO_DMACH0CTL_EN_EN 0x00000001 236 #define CRYPTO_DMACH0CTL_EN_DIS 0x00000000 237 238 //***************************************************************************** 239 // 240 // Register: CRYPTO_O_DMACH0EXTADDR 241 // 242 //***************************************************************************** 243 // Field: [31:0] ADDR 244 // 245 // Channel external address value. 246 // Holds the last updated external address after being sent to the master 247 // interface. 248 #define CRYPTO_DMACH0EXTADDR_ADDR_W 32 249 #define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF 250 #define CRYPTO_DMACH0EXTADDR_ADDR_S 0 251 252 //***************************************************************************** 253 // 254 // Register: CRYPTO_O_DMACH0LEN 255 // 256 //***************************************************************************** 257 // Field: [15:0] LEN 258 // 259 // DMA transfer length in bytes. 260 // During configuration, this register contains the DMA transfer length in 261 // bytes. During operation, it contains the last updated value of the DMA 262 // transfer length after being sent to the master interface. 263 // Note: Writing a non-zero value to this register field starts the transfer if 264 // the channel is enabled by setting DMACH0CTL.EN. 265 #define CRYPTO_DMACH0LEN_LEN_W 16 266 #define CRYPTO_DMACH0LEN_LEN_M 0x0000FFFF 267 #define CRYPTO_DMACH0LEN_LEN_S 0 268 269 //***************************************************************************** 270 // 271 // Register: CRYPTO_O_DMASTAT 272 // 273 //***************************************************************************** 274 // Field: [17] PORT_ERR 275 // 276 // Reflects possible transfer errors on the AHB port. 277 #define CRYPTO_DMASTAT_PORT_ERR 0x00020000 278 #define CRYPTO_DMASTAT_PORT_ERR_BITN 17 279 #define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 280 #define CRYPTO_DMASTAT_PORT_ERR_S 17 281 282 // Field: [1] CH1_ACTIVE 283 // 284 // This register field indicates if DMA channel 1 is active or not. 285 // 0: Not active 286 // 1: Active 287 #define CRYPTO_DMASTAT_CH1_ACTIVE 0x00000002 288 #define CRYPTO_DMASTAT_CH1_ACTIVE_BITN 1 289 #define CRYPTO_DMASTAT_CH1_ACTIVE_M 0x00000002 290 #define CRYPTO_DMASTAT_CH1_ACTIVE_S 1 291 292 // Field: [0] CH0_ACTIVE 293 // 294 // This register field indicates if DMA channel 0 is active or not. 295 // 0: Not active 296 // 1: Active 297 #define CRYPTO_DMASTAT_CH0_ACTIVE 0x00000001 298 #define CRYPTO_DMASTAT_CH0_ACTIVE_BITN 0 299 #define CRYPTO_DMASTAT_CH0_ACTIVE_M 0x00000001 300 #define CRYPTO_DMASTAT_CH0_ACTIVE_S 0 301 302 //***************************************************************************** 303 // 304 // Register: CRYPTO_O_DMASWRESET 305 // 306 //***************************************************************************** 307 // Field: [0] RESET 308 // 309 // Software reset enable 310 // 311 // 0: Disable 312 // 1: Enable (self-cleared to zero). 313 // 314 // Note: Completion of the software reset must be checked in DMASTAT.CH0_ACTIVE 315 // and DMASTAT.CH1_ACTIVE. 316 #define CRYPTO_DMASWRESET_RESET 0x00000001 317 #define CRYPTO_DMASWRESET_RESET_BITN 0 318 #define CRYPTO_DMASWRESET_RESET_M 0x00000001 319 #define CRYPTO_DMASWRESET_RESET_S 0 320 321 //***************************************************************************** 322 // 323 // Register: CRYPTO_O_DMACH1CTL 324 // 325 //***************************************************************************** 326 // Field: [1] PRIO 327 // 328 // Channel priority: 329 // 330 // A channel with high priority will be served before a channel with low 331 // priority in cases with simultaneous access requests. If both channels have 332 // the same priority access of the channels to the external port is arbitrated 333 // using a Round Robin scheme. 334 // ENUMs: 335 // HIGH Priority high 336 // LOW Priority low 337 #define CRYPTO_DMACH1CTL_PRIO 0x00000002 338 #define CRYPTO_DMACH1CTL_PRIO_BITN 1 339 #define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 340 #define CRYPTO_DMACH1CTL_PRIO_S 1 341 #define CRYPTO_DMACH1CTL_PRIO_HIGH 0x00000002 342 #define CRYPTO_DMACH1CTL_PRIO_LOW 0x00000000 343 344 // Field: [0] EN 345 // 346 // Channel enable: 347 // 348 // Note: Disabling an active channel will interrupt the DMA operation. The 349 // ongoing block transfer will be completed, but no new transfers will be 350 // requested. 351 // ENUMs: 352 // EN Channel enabled 353 // DIS Channel disabled 354 #define CRYPTO_DMACH1CTL_EN 0x00000001 355 #define CRYPTO_DMACH1CTL_EN_BITN 0 356 #define CRYPTO_DMACH1CTL_EN_M 0x00000001 357 #define CRYPTO_DMACH1CTL_EN_S 0 358 #define CRYPTO_DMACH1CTL_EN_EN 0x00000001 359 #define CRYPTO_DMACH1CTL_EN_DIS 0x00000000 360 361 //***************************************************************************** 362 // 363 // Register: CRYPTO_O_DMACH1EXTADDR 364 // 365 //***************************************************************************** 366 // Field: [31:0] ADDR 367 // 368 // Channel external address value. 369 // Holds the last updated external address after being sent to the master 370 // interface. 371 #define CRYPTO_DMACH1EXTADDR_ADDR_W 32 372 #define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF 373 #define CRYPTO_DMACH1EXTADDR_ADDR_S 0 374 375 //***************************************************************************** 376 // 377 // Register: CRYPTO_O_DMACH1LEN 378 // 379 //***************************************************************************** 380 // Field: [15:0] LEN 381 // 382 // DMA transfer length in bytes. 383 // During configuration, this register contains the DMA transfer length in 384 // bytes. During operation, it contains the last updated value of the DMA 385 // transfer length after being sent to the master interface. 386 // Note: Writing a non-zero value to this register field starts the transfer if 387 // the channel is enabled by setting DMACH1CTL.EN. 388 #define CRYPTO_DMACH1LEN_LEN_W 16 389 #define CRYPTO_DMACH1LEN_LEN_M 0x0000FFFF 390 #define CRYPTO_DMACH1LEN_LEN_S 0 391 392 //***************************************************************************** 393 // 394 // Register: CRYPTO_O_DMABUSCFG 395 // 396 //***************************************************************************** 397 // Field: [15:12] AHB_MST1_BURST_SIZE 398 // 399 // Maximum burst size that can be performed on the AHB bus 400 // ENUMs: 401 // 64_BYTE 64 bytes 402 // 32_BYTE 32 bytes 403 // 16_BYTE 16 bytes 404 // 8_BYTE 8 bytes 405 // 4_BYTE 4 bytes 406 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 407 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 408 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 409 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 410 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 411 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 412 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 413 #define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 414 415 // Field: [11] AHB_MST1_IDLE_EN 416 // 417 // Idle transfer insertion between consecutive burst transfers on AHB 418 // ENUMs: 419 // IDLE Idle transfer insertion enabled 420 // NO_IDLE Do not insert idle transfers. 421 #define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 422 #define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 423 #define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 424 #define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 425 #define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 426 #define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 427 428 // Field: [10] AHB_MST1_INCR_EN 429 // 430 // Burst length type of AHB transfer 431 // ENUMs: 432 // SPECIFIED Fixed length bursts or single transfers 433 // UNSPECIFIED Unspecified length burst transfers 434 #define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 435 #define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 436 #define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 437 #define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 438 #define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 439 #define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 440 441 // Field: [9] AHB_MST1_LOCK_EN 442 // 443 // Locked transform on AHB 444 // ENUMs: 445 // LOCKED Transfers are locked 446 // NOT_LOCKED Transfers are not locked 447 #define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 448 #define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 449 #define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 450 #define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 451 #define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 452 #define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 453 454 // Field: [8] AHB_MST1_BIGEND 455 // 456 // Endianess for the AHB master 457 // ENUMs: 458 // BIG_ENDIAN Big Endian 459 // LITTLE_ENDIAN Little Endian 460 #define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 461 #define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 462 #define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 463 #define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 464 #define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 465 #define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 466 467 //***************************************************************************** 468 // 469 // Register: CRYPTO_O_DMAPORTERR 470 // 471 //***************************************************************************** 472 // Field: [12] AHB_ERR 473 // 474 // A 1 indicates that the Crypto peripheral has detected an AHB bus error 475 #define CRYPTO_DMAPORTERR_AHB_ERR 0x00001000 476 #define CRYPTO_DMAPORTERR_AHB_ERR_BITN 12 477 #define CRYPTO_DMAPORTERR_AHB_ERR_M 0x00001000 478 #define CRYPTO_DMAPORTERR_AHB_ERR_S 12 479 480 // Field: [9] LAST_CH 481 // 482 // Indicates which channel was serviced last (channel 0 or channel 1) by the 483 // AHB master port. 484 #define CRYPTO_DMAPORTERR_LAST_CH 0x00000200 485 #define CRYPTO_DMAPORTERR_LAST_CH_BITN 9 486 #define CRYPTO_DMAPORTERR_LAST_CH_M 0x00000200 487 #define CRYPTO_DMAPORTERR_LAST_CH_S 9 488 489 //***************************************************************************** 490 // 491 // Register: CRYPTO_O_DMAHWVER 492 // 493 //***************************************************************************** 494 // Field: [27:24] HW_MAJOR_VER 495 // 496 // Major version number 497 #define CRYPTO_DMAHWVER_HW_MAJOR_VER_W 4 498 #define CRYPTO_DMAHWVER_HW_MAJOR_VER_M 0x0F000000 499 #define CRYPTO_DMAHWVER_HW_MAJOR_VER_S 24 500 501 // Field: [23:20] HW_MINOR_VER 502 // 503 // Minor version number 504 #define CRYPTO_DMAHWVER_HW_MINOR_VER_W 4 505 #define CRYPTO_DMAHWVER_HW_MINOR_VER_M 0x00F00000 506 #define CRYPTO_DMAHWVER_HW_MINOR_VER_S 20 507 508 // Field: [19:16] HW_PATCH_LVL 509 // 510 // Patch level. 511 #define CRYPTO_DMAHWVER_HW_PATCH_LVL_W 4 512 #define CRYPTO_DMAHWVER_HW_PATCH_LVL_M 0x000F0000 513 #define CRYPTO_DMAHWVER_HW_PATCH_LVL_S 16 514 515 // Field: [15:8] VER_NUM_COMPL 516 // 517 // Bit-by-bit complement of the VER_NUM field bits. 518 #define CRYPTO_DMAHWVER_VER_NUM_COMPL_W 8 519 #define CRYPTO_DMAHWVER_VER_NUM_COMPL_M 0x0000FF00 520 #define CRYPTO_DMAHWVER_VER_NUM_COMPL_S 8 521 522 // Field: [7:0] VER_NUM 523 // 524 // Version number of the DMA Controller (209) 525 #define CRYPTO_DMAHWVER_VER_NUM_W 8 526 #define CRYPTO_DMAHWVER_VER_NUM_M 0x000000FF 527 #define CRYPTO_DMAHWVER_VER_NUM_S 0 528 529 //***************************************************************************** 530 // 531 // Register: CRYPTO_O_KEYWRITEAREA 532 // 533 //***************************************************************************** 534 // Field: [7] RAM_AREA7 535 // 536 // Represents an area of 128 bits. 537 // Select the key store RAM area(s) where the key(s) needs to be written. 538 // 539 // Writing to multiple RAM locations is only possible when the selected RAM 540 // areas are sequential. 541 // ENUMs: 542 // SEL This RAM area is selected to be written 543 // NOT_SEL This RAM area is not selected to be written 544 #define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 545 #define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 546 #define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 547 #define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 548 #define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 549 #define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 550 551 // Field: [6] RAM_AREA6 552 // 553 // Represents an area of 128 bits. 554 // Select the key store RAM area(s) where the key(s) needs to be written. 555 // 556 // Writing to multiple RAM locations is only possible when the selected RAM 557 // areas are sequential. 558 // ENUMs: 559 // SEL This RAM area is selected to be written 560 // NOT_SEL This RAM area is not selected to be written 561 #define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 562 #define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 563 #define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 564 #define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 565 #define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 566 #define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 567 568 // Field: [5] RAM_AREA5 569 // 570 // Represents an area of 128 bits. 571 // Select the key store RAM area(s) where the key(s) needs to be written. 572 // 573 // Writing to multiple RAM locations is only possible when the selected RAM 574 // areas are sequential. 575 // ENUMs: 576 // SEL This RAM area is selected to be written 577 // NOT_SEL This RAM area is not selected to be written 578 #define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 579 #define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 580 #define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 581 #define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 582 #define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 583 #define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 584 585 // Field: [4] RAM_AREA4 586 // 587 // Represents an area of 128 bits. 588 // Select the key store RAM area(s) where the key(s) needs to be written. 589 // 590 // Writing to multiple RAM locations is only possible when the selected RAM 591 // areas are sequential. 592 // ENUMs: 593 // SEL This RAM area is selected to be written 594 // NOT_SEL This RAM area is not selected to be written 595 #define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 596 #define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 597 #define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 598 #define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 599 #define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 600 #define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 601 602 // Field: [3] RAM_AREA3 603 // 604 // Represents an area of 128 bits. 605 // Select the key store RAM area(s) where the key(s) needs to be written. 606 // 607 // Writing to multiple RAM locations is only possible when the selected RAM 608 // areas are sequential. 609 // ENUMs: 610 // SEL This RAM area is selected to be written 611 // NOT_SEL This RAM area is not selected to be written 612 #define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 613 #define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 614 #define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 615 #define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 616 #define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 617 #define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 618 619 // Field: [2] RAM_AREA2 620 // 621 // Represents an area of 128 bits. 622 // Select the key store RAM area(s) where the key(s) needs to be written. 623 // 624 // Writing to multiple RAM locations is only possible when the selected RAM 625 // areas are sequential. 626 // ENUMs: 627 // SEL This RAM area is selected to be written 628 // NOT_SEL This RAM area is not selected to be written 629 #define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 630 #define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 631 #define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 632 #define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 633 #define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 634 #define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 635 636 // Field: [1] RAM_AREA1 637 // 638 // Represents an area of 128 bits. 639 // Select the key store RAM area(s) where the key(s) needs to be written. 640 // 641 // Writing to multiple RAM locations is only possible when the selected RAM 642 // areas are sequential. 643 // ENUMs: 644 // SEL This RAM area is selected to be written 645 // NOT_SEL This RAM area is not selected to be written 646 #define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 647 #define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 648 #define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 649 #define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 650 #define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 651 #define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 652 653 // Field: [0] RAM_AREA0 654 // 655 // Represents an area of 128 bits. 656 // Select the key store RAM area(s) where the key(s) needs to be written. 657 // 658 // Writing to multiple RAM locations is only possible when the selected RAM 659 // areas are sequential. 660 // ENUMs: 661 // SEL This RAM area is selected to be written 662 // NOT_SEL This RAM area is not selected to be written 663 #define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 664 #define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 665 #define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 666 #define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 667 #define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 668 #define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 669 670 //***************************************************************************** 671 // 672 // Register: CRYPTO_O_KEYWRITTENAREA 673 // 674 //***************************************************************************** 675 // Field: [7] RAM_AREA_WRITTEN7 676 // 677 // On read this bit returns the key area written status. 678 // 679 // This bit can be reset by writing a 1. 680 // 681 // Note: This register will be reset on a soft reset initiated by writing to 682 // DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key 683 // store memory. 684 // ENUMs: 685 // WRITTEN This RAM area is written with valid key 686 // information 687 // NOT_WRITTEN This RAM area is not written with valid key 688 // information 689 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 690 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 691 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 692 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 693 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 694 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 695 696 // Field: [6] RAM_AREA_WRITTEN6 697 // 698 // On read this bit returns the key area written status. 699 // 700 // This bit can be reset by writing a 1. 701 // 702 // Note: This register will be reset on a soft reset initiated by writing to 703 // DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key 704 // store memory. 705 // ENUMs: 706 // WRITTEN This RAM area is written with valid key 707 // information 708 // NOT_WRITTEN This RAM area is not written with valid key 709 // information 710 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 711 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 712 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 713 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 714 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 715 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 716 717 // Field: [5] RAM_AREA_WRITTEN5 718 // 719 // On read this bit returns the key area written status. 720 // 721 // This bit can be reset by writing a 1. 722 // 723 // Note: This register will be reset on a soft reset initiated by writing to 724 // DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key 725 // store memory. 726 // ENUMs: 727 // WRITTEN This RAM area is written with valid key 728 // information 729 // NOT_WRITTEN This RAM area is not written with valid key 730 // information 731 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 732 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 733 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 734 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 735 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 736 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 737 738 // Field: [4] RAM_AREA_WRITTEN4 739 // 740 // On read this bit returns the key area written status. 741 // 742 // This bit can be reset by writing a 1. 743 // 744 // Note: This register will be reset on a soft reset initiated by writing to 745 // DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key 746 // store memory. 747 // ENUMs: 748 // WRITTEN This RAM area is written with valid key 749 // information 750 // NOT_WRITTEN This RAM area is not written with valid key 751 // information 752 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 753 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 754 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 755 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 756 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 757 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 758 759 // Field: [3] RAM_AREA_WRITTEN3 760 // 761 // On read this bit returns the key area written status. 762 // 763 // This bit can be reset by writing a 1. 764 // 765 // Note: This register will be reset on a soft reset initiated by writing to 766 // DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key 767 // store memory. 768 // ENUMs: 769 // WRITTEN This RAM area is written with valid key 770 // information 771 // NOT_WRITTEN This RAM area is not written with valid key 772 // information 773 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 774 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 775 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 776 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 777 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 778 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 779 780 // Field: [2] RAM_AREA_WRITTEN2 781 // 782 // On read this bit returns the key area written status. 783 // 784 // This bit can be reset by writing a 1. 785 // 786 // Note: This register will be reset on a soft reset initiated by writing to 787 // DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key 788 // store memory. 789 // ENUMs: 790 // WRITTEN This RAM area is written with valid key 791 // information 792 // NOT_WRITTEN This RAM area is not written with valid key 793 // information 794 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 795 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 796 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 797 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 798 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 799 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 800 801 // Field: [1] RAM_AREA_WRITTEN1 802 // 803 // On read this bit returns the key area written status. 804 // 805 // This bit can be reset by writing a 1. 806 // 807 // Note: This register will be reset on a soft reset initiated by writing to 808 // DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key 809 // store memory. 810 // ENUMs: 811 // WRITTEN This RAM area is written with valid key 812 // information 813 // NOT_WRITTEN This RAM area is not written with valid key 814 // information 815 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 816 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 817 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 818 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 819 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 820 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 821 822 // Field: [0] RAM_AREA_WRITTEN0 823 // 824 // On read this bit returns the key area written status. 825 // 826 // 827 // This bit can be reset by writing a 1. 828 // 829 // Note: This register will be reset on a soft reset initiated by writing to 830 // DMASWRESET.RESET. After a soft reset, all keys must be rewritten to the key 831 // store memory. 832 // ENUMs: 833 // WRITTEN This RAM area is written with valid key 834 // information 835 // NOT_WRITTEN This RAM area is not written with valid key 836 // information 837 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 838 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 839 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 840 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 841 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_WRITTEN 0x00000001 842 #define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_NOT_WRITTEN 0x00000000 843 844 //***************************************************************************** 845 // 846 // Register: CRYPTO_O_KEYSIZE 847 // 848 //***************************************************************************** 849 // Field: [1:0] SIZE 850 // 851 // Key size 852 // 853 // When writing to this register, KEYWRITTENAREA will be reset. 854 // 855 // Note: For the Crypto peripheral this field is fixed to 128 bits. For 856 // software compatibility KEYWRITTENAREA will be reset when writing to this 857 // register. 858 // ENUMs: 859 // 256_BIT Not supported 860 // 192_BIT Not supported 861 // 128_BIT 128 bits 862 #define CRYPTO_KEYSIZE_SIZE_W 2 863 #define CRYPTO_KEYSIZE_SIZE_M 0x00000003 864 #define CRYPTO_KEYSIZE_SIZE_S 0 865 #define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 866 #define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 867 #define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 868 869 //***************************************************************************** 870 // 871 // Register: CRYPTO_O_KEYREADAREA 872 // 873 //***************************************************************************** 874 // Field: [31] BUSY 875 // 876 // Key store operation busy status flag (read only) 877 // 878 // 0: operation is completed. 879 // 1: operation is not completed and the key store is busy. 880 #define CRYPTO_KEYREADAREA_BUSY 0x80000000 881 #define CRYPTO_KEYREADAREA_BUSY_BITN 31 882 #define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 883 #define CRYPTO_KEYREADAREA_BUSY_S 31 884 885 // Field: [3:0] RAM_AREA 886 // 887 // Selects the area of the key store RAM from where the key needs to be read 888 // that will be written to the AES engine. 889 // 890 // Only RAM areas that contain valid written keys can be selected. 891 // ENUMs: 892 // NO_RAM No RAM 893 // RAM_AREA7 RAM Area 7 894 // RAM_AREA6 RAM Area 6 895 // RAM_AREA5 RAM Area 5 896 // RAM_AREA4 RAM Area 4 897 // RAM_AREA3 RAM Area 3 898 // RAM_AREA2 RAM Area 2 899 // RAM_AREA1 RAM Area 1 900 // RAM_AREA0 RAM Area 0 901 #define CRYPTO_KEYREADAREA_RAM_AREA_W 4 902 #define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F 903 #define CRYPTO_KEYREADAREA_RAM_AREA_S 0 904 #define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 905 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 906 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 907 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 908 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 909 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 910 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 911 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 912 #define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 913 914 //***************************************************************************** 915 // 916 // Register: CRYPTO_O_AESKEY20 917 // 918 //***************************************************************************** 919 // Field: [31:0] KEY2 920 // 921 // AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, 922 // 96 ordered from the LSW entry of this 4-deep register array. 923 // The interpretation of this field depends on the crypto operation mode. 924 #define CRYPTO_AESKEY20_KEY2_W 32 925 #define CRYPTO_AESKEY20_KEY2_M 0xFFFFFFFF 926 #define CRYPTO_AESKEY20_KEY2_S 0 927 928 //***************************************************************************** 929 // 930 // Register: CRYPTO_O_AESKEY21 931 // 932 //***************************************************************************** 933 // Field: [31:0] KEY2 934 // 935 // AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, 936 // 96 ordered from the LSW entry of this 4-deep register array. 937 // The interpretation of this field depends on the crypto operation mode. 938 #define CRYPTO_AESKEY21_KEY2_W 32 939 #define CRYPTO_AESKEY21_KEY2_M 0xFFFFFFFF 940 #define CRYPTO_AESKEY21_KEY2_S 0 941 942 //***************************************************************************** 943 // 944 // Register: CRYPTO_O_AESKEY22 945 // 946 //***************************************************************************** 947 // Field: [31:0] KEY2 948 // 949 // AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, 950 // 96 ordered from the LSW entry of this 4-deep register array. 951 // The interpretation of this field depends on the crypto operation mode. 952 #define CRYPTO_AESKEY22_KEY2_W 32 953 #define CRYPTO_AESKEY22_KEY2_M 0xFFFFFFFF 954 #define CRYPTO_AESKEY22_KEY2_S 0 955 956 //***************************************************************************** 957 // 958 // Register: CRYPTO_O_AESKEY23 959 // 960 //***************************************************************************** 961 // Field: [31:0] KEY2 962 // 963 // AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, 964 // 96 ordered from the LSW entry of this 4-deep register array. 965 // The interpretation of this field depends on the crypto operation mode. 966 #define CRYPTO_AESKEY23_KEY2_W 32 967 #define CRYPTO_AESKEY23_KEY2_M 0xFFFFFFFF 968 #define CRYPTO_AESKEY23_KEY2_S 0 969 970 //***************************************************************************** 971 // 972 // Register: CRYPTO_O_AESKEY30 973 // 974 //***************************************************************************** 975 // Field: [31:0] KEY3 976 // 977 // AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, 978 // 96 ordered from the LSW entry of this 4-deep register arrary. 979 // The interpretation of this field depends on the crypto operation mode. 980 #define CRYPTO_AESKEY30_KEY3_W 32 981 #define CRYPTO_AESKEY30_KEY3_M 0xFFFFFFFF 982 #define CRYPTO_AESKEY30_KEY3_S 0 983 984 //***************************************************************************** 985 // 986 // Register: CRYPTO_O_AESKEY31 987 // 988 //***************************************************************************** 989 // Field: [31:0] KEY3 990 // 991 // AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, 992 // 96 ordered from the LSW entry of this 4-deep register arrary. 993 // The interpretation of this field depends on the crypto operation mode. 994 #define CRYPTO_AESKEY31_KEY3_W 32 995 #define CRYPTO_AESKEY31_KEY3_M 0xFFFFFFFF 996 #define CRYPTO_AESKEY31_KEY3_S 0 997 998 //***************************************************************************** 999 // 1000 // Register: CRYPTO_O_AESKEY32 1001 // 1002 //***************************************************************************** 1003 // Field: [31:0] KEY3 1004 // 1005 // AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, 1006 // 96 ordered from the LSW entry of this 4-deep register arrary. 1007 // The interpretation of this field depends on the crypto operation mode. 1008 #define CRYPTO_AESKEY32_KEY3_W 32 1009 #define CRYPTO_AESKEY32_KEY3_M 0xFFFFFFFF 1010 #define CRYPTO_AESKEY32_KEY3_S 0 1011 1012 //***************************************************************************** 1013 // 1014 // Register: CRYPTO_O_AESKEY33 1015 // 1016 //***************************************************************************** 1017 // Field: [31:0] KEY3 1018 // 1019 // AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, 1020 // 96 ordered from the LSW entry of this 4-deep register arrary. 1021 // The interpretation of this field depends on the crypto operation mode. 1022 #define CRYPTO_AESKEY33_KEY3_W 32 1023 #define CRYPTO_AESKEY33_KEY3_M 0xFFFFFFFF 1024 #define CRYPTO_AESKEY33_KEY3_S 0 1025 1026 //***************************************************************************** 1027 // 1028 // Register: CRYPTO_O_AESIV0 1029 // 1030 //***************************************************************************** 1031 // Field: [31:0] IV 1032 // 1033 // The interpretation of this field depends on the crypto operation mode. 1034 #define CRYPTO_AESIV0_IV_W 32 1035 #define CRYPTO_AESIV0_IV_M 0xFFFFFFFF 1036 #define CRYPTO_AESIV0_IV_S 0 1037 1038 //***************************************************************************** 1039 // 1040 // Register: CRYPTO_O_AESIV1 1041 // 1042 //***************************************************************************** 1043 // Field: [31:0] IV 1044 // 1045 // The interpretation of this field depends on the crypto operation mode. 1046 #define CRYPTO_AESIV1_IV_W 32 1047 #define CRYPTO_AESIV1_IV_M 0xFFFFFFFF 1048 #define CRYPTO_AESIV1_IV_S 0 1049 1050 //***************************************************************************** 1051 // 1052 // Register: CRYPTO_O_AESIV2 1053 // 1054 //***************************************************************************** 1055 // Field: [31:0] IV 1056 // 1057 // The interpretation of this field depends on the crypto operation mode. 1058 #define CRYPTO_AESIV2_IV_W 32 1059 #define CRYPTO_AESIV2_IV_M 0xFFFFFFFF 1060 #define CRYPTO_AESIV2_IV_S 0 1061 1062 //***************************************************************************** 1063 // 1064 // Register: CRYPTO_O_AESIV3 1065 // 1066 //***************************************************************************** 1067 // Field: [31:0] IV 1068 // 1069 // The interpretation of this field depends on the crypto operation mode. 1070 #define CRYPTO_AESIV3_IV_W 32 1071 #define CRYPTO_AESIV3_IV_M 0xFFFFFFFF 1072 #define CRYPTO_AESIV3_IV_S 0 1073 1074 //***************************************************************************** 1075 // 1076 // Register: CRYPTO_O_AESCTL 1077 // 1078 //***************************************************************************** 1079 // Field: [31] CONTEXT_RDY 1080 // 1081 // If 1, this status bit indicates that the context data registers can be 1082 // overwritten and the Host is permitted to write the next context. Writing a 1083 // context means writing either a mode, the crypto length or 1084 // AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length registers 1085 #define CRYPTO_AESCTL_CONTEXT_RDY 0x80000000 1086 #define CRYPTO_AESCTL_CONTEXT_RDY_BITN 31 1087 #define CRYPTO_AESCTL_CONTEXT_RDY_M 0x80000000 1088 #define CRYPTO_AESCTL_CONTEXT_RDY_S 31 1089 1090 // Field: [30] SAVED_CONTEXT_RDY 1091 // 1092 // If read as 1, this status bit indicates that an AES authentication TAG 1093 // and/or IV block(s) is/are available for the Host to retrieve. This bit is 1094 // only asserted if SAVE_CONTEXT is set to 1. The bit is mutually exclusive 1095 // with CONTEXT_RDY. 1096 // 1097 // Writing 1 clears the bit to zero, indicating the Crypto peripheral can start 1098 // its next operation. This bit is also cleared when the 4th word of the output 1099 // TAG and/or IV is read. 1100 // 1101 // Note: All other mode bit writes will be ignored when this mode bit is 1102 // written with 1. 1103 // 1104 // Note: This bit is controlled automatically by the Crypto peripheral for TAG 1105 // read DMA operations. 1106 // 1107 // For typical use, this bit does NOT need to be written, but is used for 1108 // status reading only. In this case, this status bit is automatically 1109 // maintained by the Crypto peripheral. 1110 #define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 1111 #define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 1112 #define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 1113 #define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 1114 1115 // Field: [29] SAVE_CONTEXT 1116 // 1117 // IV must be read before the AES engine can start a new operation. 1118 #define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 1119 #define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 1120 #define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 1121 #define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 1122 1123 // Field: [24:22] CCM_M 1124 // 1125 // Defines M that indicates the length of the authentication field for CCM 1126 // operations; the authentication field length equals two times the value of 1127 // CCM_M plus one. 1128 // Note: The Crypto peripheral always returns a 128-bit authentication field, 1129 // of which the M least significant bytes are valid. All values are supported. 1130 #define CRYPTO_AESCTL_CCM_M_W 3 1131 #define CRYPTO_AESCTL_CCM_M_M 0x01C00000 1132 #define CRYPTO_AESCTL_CCM_M_S 22 1133 1134 // Field: [21:19] CCM_L 1135 // 1136 // Defines L that indicates the width of the length field for CCM operations; 1137 // the length field in bytes equals the value of CMM_L plus one. All values are 1138 // supported. 1139 #define CRYPTO_AESCTL_CCM_L_W 3 1140 #define CRYPTO_AESCTL_CCM_L_M 0x00380000 1141 #define CRYPTO_AESCTL_CCM_L_S 19 1142 1143 // Field: [18] CCM 1144 // 1145 // AES-CCM mode enable. 1146 // AES-CCM is a combined mode, using AES for both authentication and 1147 // encryption. 1148 // Note: Selecting AES-CCM mode requires writing of AESDATALEN1.LEN_MSW and 1149 // AESDATALEN0.LEN_LSW after all other registers. 1150 // Note: The CTR mode bit in this register must also be set to 1 to enable 1151 // AES-CTR; selecting other AES modes than CTR mode is invalid. 1152 #define CRYPTO_AESCTL_CCM 0x00040000 1153 #define CRYPTO_AESCTL_CCM_BITN 18 1154 #define CRYPTO_AESCTL_CCM_M 0x00040000 1155 #define CRYPTO_AESCTL_CCM_S 18 1156 1157 // Field: [15] CBC_MAC 1158 // 1159 // MAC mode enable. 1160 // The DIR bit must be set to 1 for this mode. 1161 // Selecting this mode requires writing the AESDATALEN1.LEN_MSW and 1162 // AESDATALEN0.LEN_LSW registers after all other registers. 1163 #define CRYPTO_AESCTL_CBC_MAC 0x00008000 1164 #define CRYPTO_AESCTL_CBC_MAC_BITN 15 1165 #define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 1166 #define CRYPTO_AESCTL_CBC_MAC_S 15 1167 1168 // Field: [8:7] CTR_WIDTH 1169 // 1170 // Specifies the counter width for AES-CTR mode 1171 // ENUMs: 1172 // 128_BIT 128 bits 1173 // 96_BIT 96 bits 1174 // 64_BIT 64 bits 1175 // 32_BIT 32 bits 1176 #define CRYPTO_AESCTL_CTR_WIDTH_W 2 1177 #define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 1178 #define CRYPTO_AESCTL_CTR_WIDTH_S 7 1179 #define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 1180 #define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 1181 #define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 1182 #define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 1183 1184 // Field: [6] CTR 1185 // 1186 // AES-CTR mode enable 1187 // This bit must also be set for CCM, when encryption/decryption is required. 1188 #define CRYPTO_AESCTL_CTR 0x00000040 1189 #define CRYPTO_AESCTL_CTR_BITN 6 1190 #define CRYPTO_AESCTL_CTR_M 0x00000040 1191 #define CRYPTO_AESCTL_CTR_S 6 1192 1193 // Field: [5] CBC 1194 // 1195 // CBC mode enable 1196 #define CRYPTO_AESCTL_CBC 0x00000020 1197 #define CRYPTO_AESCTL_CBC_BITN 5 1198 #define CRYPTO_AESCTL_CBC_M 0x00000020 1199 #define CRYPTO_AESCTL_CBC_S 5 1200 1201 // Field: [4:3] KEY_SIZE 1202 // 1203 // This field specifies the key size. 1204 // The key size is automatically configured when a new key is loaded via the 1205 // key store module. 1206 // 00 = N/A - reserved 1207 // 01 = 128 bits 1208 // 10 = N/A - reserved 1209 // 11 = N/A - reserved 1210 // For the Crypto peripheral this field is fixed to 128 bits. 1211 #define CRYPTO_AESCTL_KEY_SIZE_W 2 1212 #define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 1213 #define CRYPTO_AESCTL_KEY_SIZE_S 3 1214 1215 // Field: [2] DIR 1216 // 1217 // Direction. 1218 // 0 : Decrypt operation is performed. 1219 // 1 : Encrypt operation is performed. 1220 // 1221 // This bit must be written with a 1 when CBC-MAC is selected. 1222 #define CRYPTO_AESCTL_DIR 0x00000004 1223 #define CRYPTO_AESCTL_DIR_BITN 2 1224 #define CRYPTO_AESCTL_DIR_M 0x00000004 1225 #define CRYPTO_AESCTL_DIR_S 2 1226 1227 // Field: [1] INPUT_RDY 1228 // 1229 // If read as 1, this status bit indicates that the 16-byte AES input buffer is 1230 // empty. The Host is permitted to write the next block of data. 1231 // 1232 // Writing a 0 clears the bit to zero and indicates that the AES engine can use 1233 // the provided input data block. 1234 // 1235 // Writing a 1 to this bit will be ignored. 1236 // 1237 // Note: For DMA operations, this bit is automatically controlled by the Crypto 1238 // peripheral. 1239 // After reset, this bit is 0. After writing a context (note 1), this bit will 1240 // become 1. 1241 // 1242 // For typical use, this bit does NOT need to be written, but is used for 1243 // status reading only. In this case, this status bit is automatically 1244 // maintained by the Crypto peripheral. 1245 #define CRYPTO_AESCTL_INPUT_RDY 0x00000002 1246 #define CRYPTO_AESCTL_INPUT_RDY_BITN 1 1247 #define CRYPTO_AESCTL_INPUT_RDY_M 0x00000002 1248 #define CRYPTO_AESCTL_INPUT_RDY_S 1 1249 1250 // Field: [0] OUTPUT_RDY 1251 // 1252 // If read as 1, this status bit indicates that an AES output block is 1253 // available to be retrieved by the Host. 1254 // 1255 // Writing a 0 clears the bit to zero and indicates that output data is read by 1256 // the Host. The AES engine can provide a next output data block. 1257 // 1258 // Writing a 1 to this bit will be ignored. 1259 // 1260 // Note: For DMA operations, this bit is automatically controlled by the Crypto 1261 // peripheral. 1262 // 1263 // For typical use, this bit does NOT need to be written, but is used for 1264 // status reading only. In this case, this status bit is automatically 1265 // maintained by the Crypto peripheral. 1266 #define CRYPTO_AESCTL_OUTPUT_RDY 0x00000001 1267 #define CRYPTO_AESCTL_OUTPUT_RDY_BITN 0 1268 #define CRYPTO_AESCTL_OUTPUT_RDY_M 0x00000001 1269 #define CRYPTO_AESCTL_OUTPUT_RDY_S 0 1270 1271 //***************************************************************************** 1272 // 1273 // Register: CRYPTO_O_AESDATALEN0 1274 // 1275 //***************************************************************************** 1276 // Field: [31:0] LEN_LSW 1277 // 1278 // Used to write the Length values to the Crypto peripheral. 1279 // 1280 // This register contains bits [31:0] of the combined data length. 1281 #define CRYPTO_AESDATALEN0_LEN_LSW_W 32 1282 #define CRYPTO_AESDATALEN0_LEN_LSW_M 0xFFFFFFFF 1283 #define CRYPTO_AESDATALEN0_LEN_LSW_S 0 1284 1285 //***************************************************************************** 1286 // 1287 // Register: CRYPTO_O_AESDATALEN1 1288 // 1289 //***************************************************************************** 1290 // Field: [28:0] LEN_MSW 1291 // 1292 // Bits [60:32] of the combined data length. 1293 // 1294 // Bits [60:0] of the crypto length registers AESDATALEN1 and AESDATALEN0 store 1295 // the cryptographic data length in bytes for all modes. Once processing with 1296 // this context is started, this length decrements to zero. Data lengths up to 1297 // (2^61 - 1) bytes are allowed. 1298 // For GCM, any value up to 2^36 - 32 bytes can be used. This is because a 1299 // 32-bit counter mode is used; the maximum number of 128-bit blocks is 2^32 - 1300 // 2, resulting in a maximum number of bytes of 2^36 - 32. 1301 // Writing to this register triggers the engine to start using this context. 1302 // This is valid for all modes except GCM and CCM. 1303 // Note: For the combined modes (GCM and CCM), this length does not include the 1304 // authentication only data; the authentication length is specified in the 1305 // AESAUTHLEN.LEN. 1306 // All modes must have a length > 0. For the combined modes, it is allowed to 1307 // have one of the lengths equal to zero. 1308 // For the basic encryption modes (ECB/CBC/CTR) it is allowed to program zero 1309 // to the length field; in that case the length is assumed infinite. 1310 // All data must be byte (8-bit) aligned for stream cipher modes; bit aligned 1311 // data streams are not supported by the Crypto peripheral. For block cipher 1312 // modes, the data length must be programmed in multiples of the block cipher 1313 // size, 16 bytes. 1314 #define CRYPTO_AESDATALEN1_LEN_MSW_W 29 1315 #define CRYPTO_AESDATALEN1_LEN_MSW_M 0x1FFFFFFF 1316 #define CRYPTO_AESDATALEN1_LEN_MSW_S 0 1317 1318 //***************************************************************************** 1319 // 1320 // Register: CRYPTO_O_AESAUTHLEN 1321 // 1322 //***************************************************************************** 1323 // Field: [31:0] LEN 1324 // 1325 // Authentication data length in bytes for combined mode, CCM only. 1326 // Supported AAD-lengths for CCM are from 0 to (216 - 28) bytes. Once 1327 // processing with this context is started, this length decrements to zero. 1328 // Writing this register triggers the engine to start using this context for 1329 // CCM. 1330 #define CRYPTO_AESAUTHLEN_LEN_W 32 1331 #define CRYPTO_AESAUTHLEN_LEN_M 0xFFFFFFFF 1332 #define CRYPTO_AESAUTHLEN_LEN_S 0 1333 1334 //***************************************************************************** 1335 // 1336 // Register: CRYPTO_O_AESDATAOUT0 1337 // 1338 //***************************************************************************** 1339 // Field: [31:0] DATA 1340 // 1341 // Data register 0 for output block data from the Crypto peripheral. 1342 // These bits = AES Output Data[31:0] of {127:0] 1343 // 1344 // For normal operations, this register is not used, since data input and 1345 // output is transferred from and to the AES engine via DMA. 1346 // 1347 // For a Host read operation, these registers contain the 128-bit output block 1348 // from the latest AES operation. Reading from a word-aligned offset within 1349 // this address range will read one word (4 bytes) of data out the 4-word deep 1350 // (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one 1351 // full block) should be read before the core will move the next block to the 1352 // data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must 1353 // be written. 1354 // For the modes with authentication (CBC-MAC, GCM and CCM), the invalid 1355 // (message) bytes/words can be written with any data. 1356 // 1357 // Note: The AAD / authentication only data is not copied to the output buffer 1358 // but only used for authentication. 1359 #define CRYPTO_AESDATAOUT0_DATA_W 32 1360 #define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF 1361 #define CRYPTO_AESDATAOUT0_DATA_S 0 1362 1363 //***************************************************************************** 1364 // 1365 // Register: CRYPTO_O_AESDATAIN0 1366 // 1367 //***************************************************************************** 1368 // Field: [31:0] DATA 1369 // 1370 // Data registers for input block data to the Crypto peripheral. 1371 // These bits = AES Input Data[31:0] of [127:0] 1372 // 1373 // For normal operations, this register is not used, since data input and 1374 // output is transferred from and to the AES engine via DMA. 1375 // 1376 // For a Host write operation, these registers must be written with the 128-bit 1377 // input block for the next AES operation. Writing at a word-aligned offset 1378 // within this address range will store the word (4 bytes) of data into the 1379 // corresponding position of 4-word deep (16 bytes = 128-bit AES block) data 1380 // input buffer. This buffer is used for the next AES operation. If the last 1381 // data block is not completely filled with valid data (see notes below), it is 1382 // allowed to write only the words with valid data. Next AES operation is 1383 // triggered by writing to AESCTL.INPUT_RDY. 1384 // 1385 // Note: AES typically operates on 128 bits block multiple input data. The CTR, 1386 // GCM and CCM modes form an exception. The last block of a CTR-mode message 1387 // may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. 1388 // For GCM/CCM, the last block of both AAD and message data may contain less 1389 // than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically 1390 // pads or masks misaligned ending data blocks with zeroes for GCM, CCM and 1391 // CBC-MAC. For CTR mode, the remaining data in an unaligned data block is 1392 // ignored. 1393 #define CRYPTO_AESDATAIN0_DATA_W 32 1394 #define CRYPTO_AESDATAIN0_DATA_M 0xFFFFFFFF 1395 #define CRYPTO_AESDATAIN0_DATA_S 0 1396 1397 //***************************************************************************** 1398 // 1399 // Register: CRYPTO_O_AESDATAOUT1 1400 // 1401 //***************************************************************************** 1402 // Field: [31:0] DATA 1403 // 1404 // Data registers for output block data from the Crypto peripheral. 1405 // These bits = AES Output Data[63:32] of [127:0] 1406 // 1407 // For normal operations, this register is not used, since data input and 1408 // output is transferred from and to the AES engine via DMA. 1409 // 1410 // For a Host read operation, these registers contain the 128-bit output block 1411 // from the latest AES operation. Reading from a word-aligned offset within 1412 // this address range will read one word (4 bytes) of data out the 4-word deep 1413 // (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one 1414 // full block) should be read before the core will move the next block to the 1415 // data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must 1416 // be written. 1417 // For the modes with authentication (CBC-MAC, GCM and CCM), the invalid 1418 // (message) bytes/words can be written with any data. 1419 // 1420 // Note: The AAD / authentication only data is not copied to the output buffer 1421 // but only used for authentication. 1422 #define CRYPTO_AESDATAOUT1_DATA_W 32 1423 #define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF 1424 #define CRYPTO_AESDATAOUT1_DATA_S 0 1425 1426 //***************************************************************************** 1427 // 1428 // Register: CRYPTO_O_AESDATAIN1 1429 // 1430 //***************************************************************************** 1431 // Field: [31:0] DATA 1432 // 1433 // Data registers for input block data to the Crypto peripheral. 1434 // These bits = AES Input Data[63:32] of [127:0] 1435 // 1436 // For normal operations, this register is not used, since data input and 1437 // output is transferred from and to the AES engine via DMA. 1438 // 1439 // For a Host write operation, these registers must be written with the 128-bit 1440 // input block for the next AES operation. Writing at a word-aligned offset 1441 // within this address range will store the word (4 bytes) of data into the 1442 // corresponding position of 4-word deep (16 bytes = 128-bit AES block) data 1443 // input buffer. This buffer is used for the next AES operation. If the last 1444 // data block is not completely filled with valid data (see notes below), it is 1445 // allowed to write only the words with valid data. Next AES operation is 1446 // triggered by writing to AESCTL.INPUT_RDY. 1447 // 1448 // Note: AES typically operates on 128 bits block multiple input data. The CTR, 1449 // GCM and CCM modes form an exception. The last block of a CTR-mode message 1450 // may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. 1451 // For GCM/CCM, the last block of both AAD and message data may contain less 1452 // than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically 1453 // pads or masks misaligned ending data blocks with zeroes for GCM, CCM and 1454 // CBC-MAC. For CTR mode, the remaining data in an unaligned data block is 1455 // ignored. 1456 #define CRYPTO_AESDATAIN1_DATA_W 32 1457 #define CRYPTO_AESDATAIN1_DATA_M 0xFFFFFFFF 1458 #define CRYPTO_AESDATAIN1_DATA_S 0 1459 1460 //***************************************************************************** 1461 // 1462 // Register: CRYPTO_O_AESDATAOUT2 1463 // 1464 //***************************************************************************** 1465 // Field: [31:0] DATA 1466 // 1467 // Data registers for output block data from the Crypto peripheral. 1468 // These bits = AES Output Data[95:64] of [127:0] 1469 // 1470 // For normal operations, this register is not used, since data input and 1471 // output is transferred from and to the AES engine via DMA. 1472 // 1473 // For a Host read operation, these registers contain the 128-bit output block 1474 // from the latest AES operation. Reading from a word-aligned offset within 1475 // this address range will read one word (4 bytes) of data out the 4-word deep 1476 // (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one 1477 // full block) should be read before the core will move the next block to the 1478 // data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must 1479 // be written. 1480 // For the modes with authentication (CBC-MAC, GCM and CCM), the invalid 1481 // (message) bytes/words can be written with any data. 1482 // 1483 // Note: The AAD / authentication only data is not copied to the output buffer 1484 // but only used for authentication. 1485 #define CRYPTO_AESDATAOUT2_DATA_W 32 1486 #define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF 1487 #define CRYPTO_AESDATAOUT2_DATA_S 0 1488 1489 //***************************************************************************** 1490 // 1491 // Register: CRYPTO_O_AESDATAIN2 1492 // 1493 //***************************************************************************** 1494 // Field: [31:0] DATA 1495 // 1496 // Data registers for input block data to the Crypto peripheral. 1497 // These bits = AES Input Data[95:64] of [127:0] 1498 // 1499 // For normal operations, this register is not used, since data input and 1500 // output is transferred from and to the AES engine via DMA. 1501 // 1502 // For a Host write operation, these registers must be written with the 128-bit 1503 // input block for the next AES operation. Writing at a word-aligned offset 1504 // within this address range will store the word (4 bytes) of data into the 1505 // corresponding position of 4-word deep (16 bytes = 128-bit AES block) data 1506 // input buffer. This buffer is used for the next AES operation. If the last 1507 // data block is not completely filled with valid data (see notes below), it is 1508 // allowed to write only the words with valid data. Next AES operation is 1509 // triggered by writing to AESCTL.INPUT_RDY. 1510 // 1511 // Note: AES typically operates on 128 bits block multiple input data. The CTR, 1512 // GCM and CCM modes form an exception. The last block of a CTR-mode message 1513 // may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. 1514 // For GCM/CCM, the last block of both AAD and message data may contain less 1515 // than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically 1516 // pads or masks misaligned ending data blocks with zeroes for GCM, CCM and 1517 // CBC-MAC. For CTR mode, the remaining data in an unaligned data block is 1518 // ignored. 1519 #define CRYPTO_AESDATAIN2_DATA_W 32 1520 #define CRYPTO_AESDATAIN2_DATA_M 0xFFFFFFFF 1521 #define CRYPTO_AESDATAIN2_DATA_S 0 1522 1523 //***************************************************************************** 1524 // 1525 // Register: CRYPTO_O_AESDATAOUT3 1526 // 1527 //***************************************************************************** 1528 // Field: [31:0] DATA 1529 // 1530 // Data registers for output block data from the Crypto peripheral. 1531 // These bits = AES Output Data[127:96] of [127:0] 1532 // 1533 // For normal operations, this register is not used, since data input and 1534 // output is transferred from and to the AES engine via DMA. 1535 // 1536 // For a Host read operation, these registers contain the 128-bit output block 1537 // from the latest AES operation. Reading from a word-aligned offset within 1538 // this address range will read one word (4 bytes) of data out the 4-word deep 1539 // (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one 1540 // full block) should be read before the core will move the next block to the 1541 // data output buffer. To empty the data output buffer, AESCTL.OUTPUT_RDY must 1542 // be written. 1543 // For the modes with authentication (CBC-MAC, GCM and CCM), the invalid 1544 // (message) bytes/words can be written with any data. 1545 // 1546 // Note: The AAD / authentication only data is not copied to the output buffer 1547 // but only used for authentication. 1548 #define CRYPTO_AESDATAOUT3_DATA_W 32 1549 #define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF 1550 #define CRYPTO_AESDATAOUT3_DATA_S 0 1551 1552 //***************************************************************************** 1553 // 1554 // Register: CRYPTO_O_AESDATAIN3 1555 // 1556 //***************************************************************************** 1557 // Field: [31:0] DATA 1558 // 1559 // Data registers for input block data to the Crypto peripheral. 1560 // These bits = AES Input Data[127:96] of [127:0] 1561 // 1562 // For normal operations, this register is not used, since data input and 1563 // output is transferred from and to the AES engine via DMA. 1564 // 1565 // For a Host write operation, these registers must be written with the 128-bit 1566 // input block for the next AES operation. Writing at a word-aligned offset 1567 // within this address range will store the word (4 bytes) of data into the 1568 // corresponding position of 4-word deep (16 bytes = 128-bit AES block) data 1569 // input buffer. This buffer is used for the next AES operation. If the last 1570 // data block is not completely filled with valid data (see notes below), it is 1571 // allowed to write only the words with valid data. Next AES operation is 1572 // triggered by writing to AESCTL.INPUT_RDY. 1573 // 1574 // Note: AES typically operates on 128 bits block multiple input data. The CTR, 1575 // GCM and CCM modes form an exception. The last block of a CTR-mode message 1576 // may contain less than 128 bits (refer to [NIST 800-38A]): 0 < n <= 128 bits. 1577 // For GCM/CCM, the last block of both AAD and message data may contain less 1578 // than 128 bits (refer to [NIST 800-38D]). The Crypto peripheral automatically 1579 // pads or masks misaligned ending data blocks with zeroes for GCM, CCM and 1580 // CBC-MAC. For CTR mode, the remaining data in an unaligned data block is 1581 // ignored. 1582 #define CRYPTO_AESDATAIN3_DATA_W 32 1583 #define CRYPTO_AESDATAIN3_DATA_M 0xFFFFFFFF 1584 #define CRYPTO_AESDATAIN3_DATA_S 0 1585 1586 //***************************************************************************** 1587 // 1588 // Register: CRYPTO_O_AESTAGOUT0 1589 // 1590 //***************************************************************************** 1591 // Field: [31:0] TAG 1592 // 1593 // This register contains the authentication TAG for the combined and 1594 // authentication-only modes. 1595 #define CRYPTO_AESTAGOUT0_TAG_W 32 1596 #define CRYPTO_AESTAGOUT0_TAG_M 0xFFFFFFFF 1597 #define CRYPTO_AESTAGOUT0_TAG_S 0 1598 1599 //***************************************************************************** 1600 // 1601 // Register: CRYPTO_O_AESTAGOUT1 1602 // 1603 //***************************************************************************** 1604 // Field: [31:0] TAG 1605 // 1606 // This register contains the authentication TAG for the combined and 1607 // authentication-only modes. 1608 #define CRYPTO_AESTAGOUT1_TAG_W 32 1609 #define CRYPTO_AESTAGOUT1_TAG_M 0xFFFFFFFF 1610 #define CRYPTO_AESTAGOUT1_TAG_S 0 1611 1612 //***************************************************************************** 1613 // 1614 // Register: CRYPTO_O_AESTAGOUT2 1615 // 1616 //***************************************************************************** 1617 // Field: [31:0] TAG 1618 // 1619 // This register contains the authentication TAG for the combined and 1620 // authentication-only modes. 1621 #define CRYPTO_AESTAGOUT2_TAG_W 32 1622 #define CRYPTO_AESTAGOUT2_TAG_M 0xFFFFFFFF 1623 #define CRYPTO_AESTAGOUT2_TAG_S 0 1624 1625 //***************************************************************************** 1626 // 1627 // Register: CRYPTO_O_AESTAGOUT3 1628 // 1629 //***************************************************************************** 1630 // Field: [31:0] TAG 1631 // 1632 // This register contains the authentication TAG for the combined and 1633 // authentication-only modes. 1634 #define CRYPTO_AESTAGOUT3_TAG_W 32 1635 #define CRYPTO_AESTAGOUT3_TAG_M 0xFFFFFFFF 1636 #define CRYPTO_AESTAGOUT3_TAG_S 0 1637 1638 //***************************************************************************** 1639 // 1640 // Register: CRYPTO_O_ALGSEL 1641 // 1642 //***************************************************************************** 1643 // Field: [31] TAG 1644 // 1645 // If this bit is cleared to 0, the DMA operation involves only data. 1646 // If this bit is set, the DMA operation includes a TAG (Authentication Result 1647 // / Digest). 1648 #define CRYPTO_ALGSEL_TAG 0x80000000 1649 #define CRYPTO_ALGSEL_TAG_BITN 31 1650 #define CRYPTO_ALGSEL_TAG_M 0x80000000 1651 #define CRYPTO_ALGSEL_TAG_S 31 1652 1653 // Field: [1] AES 1654 // 1655 // If set to 1, the AES data is loaded via DMA 1656 // Both Read and Write maximum transfer size to DMA engine is set to 16 bytes 1657 #define CRYPTO_ALGSEL_AES 0x00000002 1658 #define CRYPTO_ALGSEL_AES_BITN 1 1659 #define CRYPTO_ALGSEL_AES_M 0x00000002 1660 #define CRYPTO_ALGSEL_AES_S 1 1661 1662 // Field: [0] KEY_STORE 1663 // 1664 // If set to 1, selects the Key Store to be loaded via DMA. 1665 // The maximum transfer size to DMA engine is set to 32 bytes (however 1666 // transfers of 16, 24 and 32 bytes are allowed) 1667 #define CRYPTO_ALGSEL_KEY_STORE 0x00000001 1668 #define CRYPTO_ALGSEL_KEY_STORE_BITN 0 1669 #define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 1670 #define CRYPTO_ALGSEL_KEY_STORE_S 0 1671 1672 //***************************************************************************** 1673 // 1674 // Register: CRYPTO_O_DMAPROTCTL 1675 // 1676 //***************************************************************************** 1677 // Field: [0] EN 1678 // 1679 // Select AHB transfer protection control for DMA transfers using the key store 1680 // area as destination. 1681 // 0 : transfers use 'USER' type access. 1682 // 1 : transfers use 'PRIVILEGED' type access. 1683 #define CRYPTO_DMAPROTCTL_EN 0x00000001 1684 #define CRYPTO_DMAPROTCTL_EN_BITN 0 1685 #define CRYPTO_DMAPROTCTL_EN_M 0x00000001 1686 #define CRYPTO_DMAPROTCTL_EN_S 0 1687 1688 //***************************************************************************** 1689 // 1690 // Register: CRYPTO_O_SWRESET 1691 // 1692 //***************************************************************************** 1693 // Field: [0] RESET 1694 // 1695 // If this bit is set to 1, the following modules are reset: 1696 // - Master control internal state is reset. That includes interrupt, error 1697 // status register and result available interrupt generation FSM. 1698 // - Key store module state is reset. That includes clearing the Written Area 1699 // flags; therefore the keys must be reloaded to the key store module. 1700 // Writing 0 has no effect. 1701 // The bit is self cleared after executing the reset. 1702 #define CRYPTO_SWRESET_RESET 0x00000001 1703 #define CRYPTO_SWRESET_RESET_BITN 0 1704 #define CRYPTO_SWRESET_RESET_M 0x00000001 1705 #define CRYPTO_SWRESET_RESET_S 0 1706 1707 //***************************************************************************** 1708 // 1709 // Register: CRYPTO_O_IRQTYPE 1710 // 1711 //***************************************************************************** 1712 // Field: [0] IEN 1713 // 1714 // Interrupt enable. This bit must be set to 1 to enable interrupts from the 1715 // Crypto peripheral. 1716 // 0 : All interrupts are disabled enabled. 1717 // 1 : All interrupts are enabled. 1718 #define CRYPTO_IRQTYPE_IEN 0x00000001 1719 #define CRYPTO_IRQTYPE_IEN_BITN 0 1720 #define CRYPTO_IRQTYPE_IEN_M 0x00000001 1721 #define CRYPTO_IRQTYPE_IEN_S 0 1722 1723 //***************************************************************************** 1724 // 1725 // Register: CRYPTO_O_IRQEN 1726 // 1727 //***************************************************************************** 1728 // Field: [1] DMA_IN_DONE 1729 // 1730 // This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ. 1731 #define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 1732 #define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 1733 #define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 1734 #define CRYPTO_IRQEN_DMA_IN_DONE_S 1 1735 1736 // Field: [0] RESULT_AVAIL 1737 // 1738 // This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ. 1739 #define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 1740 #define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 1741 #define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 1742 #define CRYPTO_IRQEN_RESULT_AVAIL_S 0 1743 1744 //***************************************************************************** 1745 // 1746 // Register: CRYPTO_O_IRQCLR 1747 // 1748 //***************************************************************************** 1749 // Field: [31] DMA_BUS_ERR 1750 // 1751 // If 1 is written to this bit, IRQSTAT.DMA_BUS_ERR is cleared. 1752 #define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 1753 #define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 1754 #define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 1755 #define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 1756 1757 // Field: [30] KEY_ST_WR_ERR 1758 // 1759 // If 1 is written to this bit, IRQSTAT.KEY_ST_WR_ERR is cleared. 1760 #define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 1761 #define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 1762 #define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 1763 #define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 1764 1765 // Field: [29] KEY_ST_RD_ERR 1766 // 1767 // If 1 is written to this bit, IRQSTAT.KEY_ST_RD_ERR is cleared. 1768 #define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 1769 #define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 1770 #define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 1771 #define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 1772 1773 // Field: [1] DMA_IN_DONE 1774 // 1775 // If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared. 1776 #define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 1777 #define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 1778 #define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 1779 #define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 1780 1781 // Field: [0] RESULT_AVAIL 1782 // 1783 // If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared. 1784 #define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 1785 #define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 1786 #define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 1787 #define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 1788 1789 //***************************************************************************** 1790 // 1791 // Register: CRYPTO_O_IRQSET 1792 // 1793 //***************************************************************************** 1794 // Field: [1] DMA_IN_DONE 1795 // 1796 // If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set. 1797 // Writing 0 has no effect. 1798 #define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 1799 #define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 1800 #define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 1801 #define CRYPTO_IRQSET_DMA_IN_DONE_S 1 1802 1803 // Field: [0] RESULT_AVAIL 1804 // 1805 // If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set. 1806 // Writing 0 has no effect. 1807 #define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 1808 #define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 1809 #define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 1810 #define CRYPTO_IRQSET_RESULT_AVAIL_S 0 1811 1812 //***************************************************************************** 1813 // 1814 // Register: CRYPTO_O_IRQSTAT 1815 // 1816 //***************************************************************************** 1817 // Field: [31] DMA_BUS_ERR 1818 // 1819 // This bit is set when a DMA bus error is detected during a DMA operation. The 1820 // value of this register is held until it is cleared via IRQCLR.DMA_BUS_ERR 1821 // Note: This error is asserted if an error is detected on the AHB master 1822 // interface during a DMA operation. 1823 // Note: This is not an interrupt source. 1824 #define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 1825 #define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 1826 #define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 1827 #define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 1828 1829 // Field: [30] KEY_ST_WR_ERR 1830 // 1831 // This bit is set when a write error is detected during the DMA write 1832 // operation to the key store memory. The value of this register is held until 1833 // it is cleared via IRQCLR.KEY_ST_WR_ERR 1834 // Note: This error is asserted if a DMA operation does not cover a full key 1835 // area or more areas are written than expected. 1836 // Note: This is not an interrupt source. 1837 #define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 1838 #define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 1839 #define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 1840 #define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 1841 1842 // Field: [29] KEY_ST_RD_ERR 1843 // 1844 // This bit will be set when a read error is detected during the read of a key 1845 // from the key store, while copying it to the AES engine. The value of this 1846 // register is held until it is cleared via IRQCLR.KEY_ST_RD_ERR. 1847 // Note: This error is asserted if a key location is selected in the key store 1848 // that is not available. 1849 // Note: This is not an interrupt source. 1850 #define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 1851 #define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 1852 #define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 1853 #define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 1854 1855 // Field: [1] DMA_IN_DONE 1856 // 1857 // This bit returns the status of DMA data in done interrupt. 1858 #define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 1859 #define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 1860 #define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 1861 #define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 1862 1863 // Field: [0] RESULT_AVAIL 1864 // 1865 // This bit is set high when the Crypto peripheral has a result available. 1866 #define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 1867 #define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 1868 #define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 1869 #define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 1870 1871 //***************************************************************************** 1872 // 1873 // Register: CRYPTO_O_HWVER 1874 // 1875 //***************************************************************************** 1876 // Field: [27:24] HW_MAJOR_VER 1877 // 1878 // Major version number 1879 #define CRYPTO_HWVER_HW_MAJOR_VER_W 4 1880 #define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 1881 #define CRYPTO_HWVER_HW_MAJOR_VER_S 24 1882 1883 // Field: [23:20] HW_MINOR_VER 1884 // 1885 // Minor version number 1886 #define CRYPTO_HWVER_HW_MINOR_VER_W 4 1887 #define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 1888 #define CRYPTO_HWVER_HW_MINOR_VER_S 20 1889 1890 // Field: [19:16] HW_PATCH_LVL 1891 // 1892 // Patch level, starts at 0 at first delivery of this version. 1893 #define CRYPTO_HWVER_HW_PATCH_LVL_W 4 1894 #define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 1895 #define CRYPTO_HWVER_HW_PATCH_LVL_S 16 1896 1897 // Field: [15:8] VER_NUM_COMPL 1898 // 1899 // These bits simply contain the complement of VER_NUM (0x87), used by a driver 1900 // to ascertain that the Crypto peripheral register is indeed read. 1901 #define CRYPTO_HWVER_VER_NUM_COMPL_W 8 1902 #define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 1903 #define CRYPTO_HWVER_VER_NUM_COMPL_S 8 1904 1905 // Field: [7:0] VER_NUM 1906 // 1907 // The version number for the Crypto peripheral, this field contains the value 1908 // 120 (decimal) or 0x78. 1909 #define CRYPTO_HWVER_VER_NUM_W 8 1910 #define CRYPTO_HWVER_VER_NUM_M 0x000000FF 1911 #define CRYPTO_HWVER_VER_NUM_S 0 1912 1913 1914 #endif // __CRYPTO__ 1915