1 /*
2 * @brief LPC15xx DMA chip driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2013
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __DMA_15XX_H_
33 #define __DMA_15XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /** @defgroup DMA_15XX CHIP: LPC15xx DMA Controller driver
40 * @ingroup CHIP_15XX_Drivers
41 * @{
42 */
43
44 /**
45 * @brief DMA Controller shared registers structure
46 */
47 typedef struct { /*!< DMA shared registers structure */
48 __IO uint32_t ENABLESET; /*!< DMA Channel Enable read and Set for all DMA channels */
49 __I uint32_t RESERVED0;
50 __O uint32_t ENABLECLR; /*!< DMA Channel Enable Clear for all DMA channels */
51 __I uint32_t RESERVED1;
52 __I uint32_t ACTIVE; /*!< DMA Channel Active status for all DMA channels */
53 __I uint32_t RESERVED2;
54 __I uint32_t BUSY; /*!< DMA Channel Busy status for all DMA channels */
55 __I uint32_t RESERVED3;
56 __IO uint32_t ERRINT; /*!< DMA Error Interrupt status for all DMA channels */
57 __I uint32_t RESERVED4;
58 __IO uint32_t INTENSET; /*!< DMA Interrupt Enable read and Set for all DMA channels */
59 __I uint32_t RESERVED5;
60 __O uint32_t INTENCLR; /*!< DMA Interrupt Enable Clear for all DMA channels */
61 __I uint32_t RESERVED6;
62 __IO uint32_t INTA; /*!< DMA Interrupt A status for all DMA channels */
63 __I uint32_t RESERVED7;
64 __IO uint32_t INTB; /*!< DMA Interrupt B status for all DMA channels */
65 __I uint32_t RESERVED8;
66 __O uint32_t SETVALID; /*!< DMA Set ValidPending control bits for all DMA channels */
67 __I uint32_t RESERVED9;
68 __O uint32_t SETTRIG; /*!< DMA Set Trigger control bits for all DMA channels */
69 __I uint32_t RESERVED10;
70 __O uint32_t ABORT; /*!< DMA Channel Abort control for all DMA channels */
71 } LPC_DMA_COMMON_T;
72
73 /**
74 * @brief DMA Controller shared registers structure
75 */
76 typedef struct { /*!< DMA channel register structure */
77 __IO uint32_t CFG; /*!< DMA Configuration register */
78 __I uint32_t CTLSTAT; /*!< DMA Control and status register */
79 __IO uint32_t XFERCFG; /*!< DMA Transfer configuration register */
80 __I uint32_t RESERVED;
81 } LPC_DMA_CHANNEL_T;
82
83 /* DMA channel mapping - each channel is mapped to an individual peripheral
84 and direction or a DMA imput mux trigger */
85 typedef enum {
86 DMAREQ_USART0_RX = 0, /*!< USART0 receive DMA channel */
87 DMA_CH0 = DMAREQ_USART0_RX,
88 DMAREQ_USART0_TX, /*!< USART0 transmit DMA channel */
89 DMA_CH1 = DMAREQ_USART0_TX,
90 DMAREQ_USART1_RX, /*!< USART1 receive DMA channel */
91 DMA_CH2 = DMAREQ_USART1_RX,
92 DMAREQ_USART1_TX, /*!< USART1 transmit DMA channel */
93 DMA_CH3 = DMAREQ_USART1_TX,
94 DMAREQ_USART2_RX, /*!< USART2 receive DMA channel */
95 DMA_CH4 = DMAREQ_USART2_RX,
96 DMAREQ_USART2_TX, /*!< USART2 transmit DMA channel */
97 DMA_CH5 = DMAREQ_USART2_TX,
98 DMAREQ_SPI0_RX, /*!< SSP0 receive DMA channel */
99 DMA_CH6 = DMAREQ_SPI0_RX,
100 DMAREQ_SPI0_TX, /*!< SSP0 transmit DMA channel */
101 DMA_CH7 = DMAREQ_SPI0_TX,
102 DMAREQ_SPI1_RX, /*!< SSP1 receive DMA channel */
103 DMA_CH8 = DMAREQ_SPI1_RX,
104 DMAREQ_SPI1_TX, /*!< SSP1 transmit DMA channel */
105 DMA_CH9 = DMAREQ_SPI1_TX,
106 DMAREQ_I2C0_SLV, /*!< I2C0 slave DMA channel */
107 DMA_CH10 = DMAREQ_I2C0_SLV,
108 DMAREQ_I2C0_MST, /*!< I2C0 master DMA channel */
109 DMA_CH11 = DMAREQ_I2C0_MST,
110 DMAREQ_I2C0_MONITOR, /*!< I2C0 monitor DMA channel */
111 DMA_CH12 = DMAREQ_I2C0_MONITOR,
112 DMAREQ_DAC_IRQ, /*!< DAC DMA channel */
113 DMA_CH13 = DMAREQ_DAC_IRQ,
114 DMAREQ_RESERVED_14,
115 DMA_CH14 = DMAREQ_RESERVED_14,
116 DMAREQ_RESERVED_15,
117 DMA_CH15 = DMAREQ_RESERVED_15,
118 DMAREQ_RESERVED_16,
119 DMA_CH16 = DMAREQ_RESERVED_16,
120 DMAREQ_RESERVED_17,
121 DMA_CH17 = DMAREQ_RESERVED_17
122 } DMA_CHID_T;
123
124 /* On LPC15xx, Max DMA channel is 18 */
125 #define MAX_DMA_CHANNEL (DMA_CH17 + 1)
126
127 /**
128 * @brief DMA Controller register block structure
129 */
130 typedef struct { /*!< DMA Structure */
131 __IO uint32_t CTRL; /*!< DMA control register */
132 __I uint32_t INTSTAT; /*!< DMA Interrupt status register */
133 __IO uint32_t SRAMBASE; /*!< DMA SRAM address of the channel configuration table */
134 __I uint32_t RESERVED2[5];
135 LPC_DMA_COMMON_T DMACOMMON[1]; /*!< DMA shared channel (common) registers */
136 __I uint32_t RESERVED0[225];
137 LPC_DMA_CHANNEL_T DMACH[MAX_DMA_CHANNEL]; /*!< DMA channel registers */
138 } LPC_DMA_T;
139
140 /** @defgroup DMA_COMMONDRV_15XX CHIP: LPC15xx DMA Controller driver common functions
141 * @{
142 */
143
144 /**
145 * @brief Initialize DMA controller
146 * @param pDMA : The base of DMA controller on the chip
147 * @return Nothing
148 */
Chip_DMA_Init(LPC_DMA_T * pDMA)149 STATIC INLINE void Chip_DMA_Init(LPC_DMA_T *pDMA)
150 {
151 (void) pDMA;
152 Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_DMA);
153 Chip_SYSCTL_PeriphReset(RESET_DMA);
154 }
155
156 /**
157 * @brief De-Initialize DMA controller
158 * @param pDMA : The base of DMA controller on the chip
159 * @return Nothing
160 */
Chip_DMA_DeInit(LPC_DMA_T * pDMA)161 STATIC INLINE void Chip_DMA_DeInit(LPC_DMA_T *pDMA)
162 {
163 (void) pDMA;
164 Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_DMA);
165 }
166
167 /**
168 * @brief Enable DMA controller
169 * @param pDMA : The base of DMA controller on the chip
170 * @return Nothing
171 */
Chip_DMA_Enable(LPC_DMA_T * pDMA)172 STATIC INLINE void Chip_DMA_Enable(LPC_DMA_T *pDMA)
173 {
174 pDMA->CTRL = 1;
175 }
176
177 /**
178 * @brief Disable DMA controller
179 * @param pDMA : The base of DMA controller on the chip
180 * @return Nothing
181 */
Chip_DMA_Disable(LPC_DMA_T * pDMA)182 STATIC INLINE void Chip_DMA_Disable(LPC_DMA_T *pDMA)
183 {
184 pDMA->CTRL = 0;
185 }
186
187 /* DMA interrupt status bits (common) */
188 #define DMA_INTSTAT_ACTIVEINT 0x2 /*!< Summarizes whether any enabled interrupts are pending */
189 #define DMA_INTSTAT_ACTIVEERRINT 0x4 /*!< Summarizes whether any error interrupts are pending */
190
191 /**
192 * @brief Get pending interrupt or error interrupts
193 * @param pDMA : The base of DMA controller on the chip
194 * @return An Or'ed value of DMA_INTSTAT_* types
195 * @note If any DMA channels have an active interrupt or error interrupt
196 * pending, this functional will a common status that applies to all
197 * channels.
198 */
Chip_DMA_GetIntStatus(LPC_DMA_T * pDMA)199 STATIC INLINE uint32_t Chip_DMA_GetIntStatus(LPC_DMA_T *pDMA)
200 {
201 return pDMA->INTSTAT;
202 }
203
204 /* DMA channel source/address/next descriptor */
205 typedef struct {
206 uint32_t xfercfg; /*!< Transfer configuration (only used in linked lists and ping-pong configs) */
207 uint32_t source; /*!< DMA transfer source end address */
208 uint32_t dest; /*!< DMA transfer desintation end address */
209 uint32_t next; /*!< Link to next DMA descriptor, must be 16 byte aligned */
210 } DMA_CHDESC_T;
211
212 /* DMA SRAM table - this can be optionally used with the Chip_DMA_SetSRAMBase()
213 function if a DMA SRAM table is needed. */
214 extern DMA_CHDESC_T Chip_DMA_Table[MAX_DMA_CHANNEL];
215
216 /**
217 * @brief Set DMA controller SRAM base address
218 * @param pDMA : The base of DMA controller on the chip
219 * @param base : The base address where the DMA descriptors will be stored
220 * @return Nothing
221 * @note A 288 byte block of memory aligned on a 512 byte boundary must be
222 * provided for this function. It sets the base address used for
223 * DMA descriptor table (18 descriptors total that use 16 bytes each).<br>
224 *
225 * A pre-defined table with correct alignment can be used for this
226 * function by calling Chip_DMA_SetSRAMBase(LPC_DMA, DMA_ADDR(Chip_DMA_Table));
227 */
Chip_DMA_SetSRAMBase(LPC_DMA_T * pDMA,uint32_t base)228 STATIC INLINE void Chip_DMA_SetSRAMBase(LPC_DMA_T *pDMA, uint32_t base)
229 {
230 pDMA->SRAMBASE = base;
231 }
232
233 /**
234 * @brief Returns DMA controller SRAM base address
235 * @param pDMA : The base of DMA controller on the chip
236 * @return The base address where the DMA descriptors are stored
237 */
Chip_DMA_GetSRAMBase(LPC_DMA_T * pDMA)238 STATIC INLINE uint32_t Chip_DMA_GetSRAMBase(LPC_DMA_T *pDMA)
239 {
240 return pDMA->SRAMBASE;
241 }
242
243 /**
244 * @}
245 */
246
247 /** @defgroup DMA_COMMON_15XX CHIP: LPC15xx DMA Controller driver common channel functions
248 * @{
249 */
250
251 /**
252 * @brief Enables a single DMA channel
253 * @param pDMA : The base of DMA controller on the chip
254 * @param ch : DMA channel ID
255 * @return Nothing
256 */
Chip_DMA_EnableChannel(LPC_DMA_T * pDMA,DMA_CHID_T ch)257 STATIC INLINE void Chip_DMA_EnableChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
258 {
259 pDMA->DMACOMMON[0].ENABLESET = (1 << ch);
260 }
261
262 /**
263 * @brief Disables a single DMA channel
264 * @param pDMA : The base of DMA controller on the chip
265 * @param ch : DMA channel ID
266 * @return Nothing
267 */
Chip_DMA_DisableChannel(LPC_DMA_T * pDMA,DMA_CHID_T ch)268 STATIC INLINE void Chip_DMA_DisableChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
269 {
270 pDMA->DMACOMMON[0].ENABLECLR = (1 << ch);
271 }
272
273 /**
274 * @brief Returns all enabled DMA channels
275 * @param pDMA : The base of DMA controller on the chip
276 * @return An Or'ed value of all enabled DMA channels (0 - 17)
277 * @note A high values in bits 0 .. 17 in the return values indicates
278 * that the channel for that bit (bit 0 = channel 0, bit 1 -
279 * channel 1, etc.) is enabled. A low state is disabled.
280 */
Chip_DMA_GetEnabledChannels(LPC_DMA_T * pDMA)281 STATIC INLINE uint32_t Chip_DMA_GetEnabledChannels(LPC_DMA_T *pDMA)
282 {
283 return pDMA->DMACOMMON[0].ENABLESET;
284 }
285
286 /**
287 * @brief Returns all active DMA channels
288 * @param pDMA : The base of DMA controller on the chip
289 * @return An Or'ed value of all active DMA channels (0 - 17)
290 * @note A high values in bits 0 .. 17 in the return values indicates
291 * that the channel for that bit (bit 0 = channel 0, bit 1 -
292 * channel 1, etc.) is active. A low state is inactive. A active
293 * channel indicates that a DMA operation has been started but
294 * not yet fully completed.
295 */
Chip_DMA_GetActiveChannels(LPC_DMA_T * pDMA)296 STATIC INLINE uint32_t Chip_DMA_GetActiveChannels(LPC_DMA_T *pDMA)
297 {
298 return pDMA->DMACOMMON[0].ACTIVE;
299 }
300
301 /**
302 * @brief Returns all busy DMA channels
303 * @param pDMA : The base of DMA controller on the chip
304 * @return An Or'ed value of all busy DMA channels (0 - 17)
305 * @note A high values in bits 0 .. 17 in the return values indicates
306 * that the channel for that bit (bit 0 = channel 0, bit 1 -
307 * channel 1, etc.) is busy. A low state is not busy. A DMA
308 * channel is considered busy when there is any operation
309 * related to that channel in the DMA controller�s internal
310 * pipeline.
311 */
Chip_DMA_GetBusyChannels(LPC_DMA_T * pDMA)312 STATIC INLINE uint32_t Chip_DMA_GetBusyChannels(LPC_DMA_T *pDMA)
313 {
314 return pDMA->DMACOMMON[0].BUSY;
315 }
316
317 /**
318 * @brief Returns pending error interrupt status for all DMA channels
319 * @param pDMA : The base of DMA controller on the chip
320 * @return An Or'ed value of all channels (0 - 17) error interrupt status
321 * @note A high values in bits 0 .. 17 in the return values indicates
322 * that the channel for that bit (bit 0 = channel 0, bit 1 -
323 * channel 1, etc.) has a pending error interrupt. A low state
324 * indicates no error interrupt.
325 */
Chip_DMA_GetErrorIntChannels(LPC_DMA_T * pDMA)326 STATIC INLINE uint32_t Chip_DMA_GetErrorIntChannels(LPC_DMA_T *pDMA)
327 {
328 return pDMA->DMACOMMON[0].ERRINT;
329 }
330
331 /**
332 * @brief Clears a pending error interrupt status for a single DMA channel
333 * @param pDMA : The base of DMA controller on the chip
334 * @param ch : DMA channel ID
335 * @return Nothing
336 */
Chip_DMA_ClearErrorIntChannel(LPC_DMA_T * pDMA,DMA_CHID_T ch)337 STATIC INLINE void Chip_DMA_ClearErrorIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
338 {
339 pDMA->DMACOMMON[0].ERRINT = (1 << ch);
340 }
341
342 /**
343 * @brief Enables a single DMA channel's interrupt used in common DMA interrupt
344 * @param pDMA : The base of DMA controller on the chip
345 * @param ch : DMA channel ID
346 * @return Nothing
347 */
Chip_DMA_EnableIntChannel(LPC_DMA_T * pDMA,DMA_CHID_T ch)348 STATIC INLINE void Chip_DMA_EnableIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
349 {
350 pDMA->DMACOMMON[0].INTENSET = (1 << ch);
351 }
352
353 /**
354 * @brief Disables a single DMA channel's interrupt used in common DMA interrupt
355 * @param pDMA : The base of DMA controller on the chip
356 * @param ch : DMA channel ID
357 * @return Nothing
358 */
Chip_DMA_DisableIntChannel(LPC_DMA_T * pDMA,DMA_CHID_T ch)359 STATIC INLINE void Chip_DMA_DisableIntChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
360 {
361 pDMA->DMACOMMON[0].INTENCLR = (1 << ch);
362 }
363
364 /**
365 * @brief Returns all enabled interrupt channels
366 * @param pDMA : The base of DMA controller on the chip
367 * @return Nothing
368 * @note A high values in bits 0 .. 17 in the return values indicates
369 * that the channel for that bit (bit 0 = channel 0, bit 1 -
370 * channel 1, etc.) has an enabled interrupt for the channel.
371 * A low state indicates that the DMA channel will not contribute
372 * to the common DMA interrupt status.
373 */
Chip_DMA_GetEnableIntChannels(LPC_DMA_T * pDMA)374 STATIC INLINE uint32_t Chip_DMA_GetEnableIntChannels(LPC_DMA_T *pDMA)
375 {
376 return pDMA->DMACOMMON[0].INTENSET;
377 }
378
379 /**
380 * @brief Returns active A interrupt status for all channels
381 * @param pDMA : The base of DMA controller on the chip
382 * @return Nothing
383 * @note A high values in bits 0 .. 17 in the return values indicates
384 * that the channel for that bit (bit 0 = channel 0, bit 1 -
385 * channel 1, etc.) has an active A interrupt for the channel.
386 * A low state indicates that the A interrupt is not active.
387 */
Chip_DMA_GetActiveIntAChannels(LPC_DMA_T * pDMA)388 STATIC INLINE uint32_t Chip_DMA_GetActiveIntAChannels(LPC_DMA_T *pDMA)
389 {
390 return pDMA->DMACOMMON[0].INTA;
391 }
392
393 /**
394 * @brief Clears active A interrupt status for a single channel
395 * @param pDMA : The base of DMA controller on the chip
396 * @param ch : DMA channel ID
397 * @return Nothing
398 */
Chip_DMA_ClearActiveIntAChannel(LPC_DMA_T * pDMA,DMA_CHID_T ch)399 STATIC INLINE void Chip_DMA_ClearActiveIntAChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
400 {
401 pDMA->DMACOMMON[0].INTA = (1 << ch);
402 }
403
404 /**
405 * @brief Returns active B interrupt status for all channels
406 * @param pDMA : The base of DMA controller on the chip
407 * @return Nothing
408 * @note A high values in bits 0 .. 17 in the return values indicates
409 * that the channel for that bit (bit 0 = channel 0, bit 1 -
410 * channel 1, etc.) has an active B interrupt for the channel.
411 * A low state indicates that the B interrupt is not active.
412 */
Chip_DMA_GetActiveIntBChannels(LPC_DMA_T * pDMA)413 STATIC INLINE uint32_t Chip_DMA_GetActiveIntBChannels(LPC_DMA_T *pDMA)
414 {
415 return pDMA->DMACOMMON[0].INTB;
416 }
417
418 /**
419 * @brief Clears active B interrupt status for a single channel
420 * @param pDMA : The base of DMA controller on the chip
421 * @param ch : DMA channel ID
422 * @return Nothing
423 */
Chip_DMA_ClearActiveIntBChannel(LPC_DMA_T * pDMA,DMA_CHID_T ch)424 STATIC INLINE void Chip_DMA_ClearActiveIntBChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
425 {
426 pDMA->DMACOMMON[0].INTB = (1 << ch);
427 }
428
429 /**
430 * @brief Sets the VALIDPENDING control bit for a single channel
431 * @param pDMA : The base of DMA controller on the chip
432 * @param ch : DMA channel ID
433 * @return Nothing
434 * @note See the User Manual for more information for what this bit does.
435 *
436 */
Chip_DMA_SetValidChannel(LPC_DMA_T * pDMA,DMA_CHID_T ch)437 STATIC INLINE void Chip_DMA_SetValidChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
438 {
439 pDMA->DMACOMMON[0].SETVALID = (1 << ch);
440 }
441
442 /**
443 * @brief Sets the TRIG bit for a single channel
444 * @param pDMA : The base of DMA controller on the chip
445 * @param ch : DMA channel ID
446 * @return Nothing
447 * @note See the User Manual for more information for what this bit does.
448 */
Chip_DMA_SetTrigChannel(LPC_DMA_T * pDMA,DMA_CHID_T ch)449 STATIC INLINE void Chip_DMA_SetTrigChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
450 {
451 pDMA->DMACOMMON[0].SETTRIG = (1 << ch);
452 }
453
454 /**
455 * @brief Aborts a DMA operation for a single channel
456 * @param pDMA : The base of DMA controller on the chip
457 * @param ch : DMA channel ID
458 * @return Nothing
459 * @note To abort a channel, the channel should first be disabled. Then wait
460 * until the channel is no longer busy by checking the corresponding
461 * bit in BUSY. Finally, abort the channel operation. This prevents the
462 * channel from restarting an incomplete operation when it is enabled
463 * again.
464 */
Chip_DMA_AbortChannel(LPC_DMA_T * pDMA,DMA_CHID_T ch)465 STATIC INLINE void Chip_DMA_AbortChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
466 {
467 pDMA->DMACOMMON[0].ABORT = (1 << ch);
468 }
469
470 /**
471 * @}
472 */
473
474 /** @defgroup DMA_CHANNEL_15XX CHIP: LPC15xx DMA Controller driver channel specific functions
475 * @{
476 */
477
478 /* Support macro for DMA_CHDESC_T */
479 #define DMA_ADDR(addr) ((uint32_t) (addr))
480
481 /* Support definitions for setting the configuration of a DMA channel. You
482 will need to get more information on these options from the User manual. */
483 #define DMA_CFG_PERIPHREQEN (1 << 0) /*!< Enables Peripheral DMA requests */
484 #define DMA_CFG_HWTRIGEN (1 << 1) /*!< Use hardware triggering via imput mux */
485 #define DMA_CFG_TRIGPOL_LOW (0 << 4) /*!< Hardware trigger is active low or falling edge */
486 #define DMA_CFG_TRIGPOL_HIGH (1 << 4) /*!< Hardware trigger is active high or rising edge */
487 #define DMA_CFG_TRIGTYPE_EDGE (0 << 5) /*!< Hardware trigger is edge triggered */
488 #define DMA_CFG_TRIGTYPE_LEVEL (1 << 5) /*!< Hardware trigger is level triggered */
489 #define DMA_CFG_TRIGBURST_SNGL (0 << 6) /*!< Single transfer. Hardware trigger causes a single transfer */
490 #define DMA_CFG_TRIGBURST_BURST (1 << 6) /*!< Burst transfer (see UM) */
491 #define DMA_CFG_BURSTPOWER_1 (0 << 8) /*!< Set DMA burst size to 1 transfer */
492 #define DMA_CFG_BURSTPOWER_2 (1 << 8) /*!< Set DMA burst size to 2 transfers */
493 #define DMA_CFG_BURSTPOWER_4 (2 << 8) /*!< Set DMA burst size to 4 transfers */
494 #define DMA_CFG_BURSTPOWER_8 (3 << 8) /*!< Set DMA burst size to 8 transfers */
495 #define DMA_CFG_BURSTPOWER_16 (4 << 8) /*!< Set DMA burst size to 16 transfers */
496 #define DMA_CFG_BURSTPOWER_32 (5 << 8) /*!< Set DMA burst size to 32 transfers */
497 #define DMA_CFG_BURSTPOWER_64 (6 << 8) /*!< Set DMA burst size to 64 transfers */
498 #define DMA_CFG_BURSTPOWER_128 (7 << 8) /*!< Set DMA burst size to 128 transfers */
499 #define DMA_CFG_BURSTPOWER_256 (8 << 8) /*!< Set DMA burst size to 256 transfers */
500 #define DMA_CFG_BURSTPOWER_512 (9 << 8) /*!< Set DMA burst size to 512 transfers */
501 #define DMA_CFG_BURSTPOWER_1024 (10 << 8) /*!< Set DMA burst size to 1024 transfers */
502 #define DMA_CFG_BURSTPOWER(n) ((n) << 8) /*!< Set DMA burst size to 2^n transfers, max n=10 */
503 #define DMA_CFG_SRCBURSTWRAP (1 << 14) /*!< Source burst wrapping is enabled for this DMA channel */
504 #define DMA_CFG_DSTBURSTWRAP (1 << 15) /*!< Destination burst wrapping is enabled for this DMA channel */
505 #define DMA_CFG_CHPRIORITY(p) ((p) << 16) /*!< Sets DMA channel priority, min 0 (highest), max 3 (lowest) */
506
507 /**
508 * @brief Setup a DMA channel configuration
509 * @param pDMA : The base of DMA controller on the chip
510 * @param ch : DMA channel ID
511 * @param cfg : An Or'ed value of DMA_CFG_* values that define the channel's configuration
512 * @return Nothing
513 * @note This function sets up all configurable options for the DMA channel.
514 * These options are usually set once for a channel and then unchanged.<br>
515 *
516 * The following example show how to configure the channel for peripheral
517 * DMA requests, burst transfer size of 1 (in 'transfers', not bytes),
518 * continuous reading of the same source address, incrementing destination
519 * address, and highest channel priority.<br>
520 * Example: Chip_DMA_SetupChannelConfig(pDMA, SSP0_RX_DMA,
521 * (DMA_CFG_PERIPHREQEN | DMA_CFG_TRIGBURST_BURST | DMA_CFG_BURSTPOWER_1 |
522 * DMA_CFG_SRCBURSTWRAP | DMA_CFG_CHPRIORITY(0)));<br>
523 *
524 * The following example show how to configure the channel for an external
525 * trigger from the imput mux with low edge polarity, a burst transfer size of 8,
526 * incrementing source and destination addresses, and lowest channel
527 * priority.<br>
528 * Example: Chip_DMA_SetupChannelConfig(pDMA, DMA_CH14,
529 * (DMA_CFG_HWTRIGEN | DMA_CFG_TRIGPOL_LOW | DMA_CFG_TRIGTYPE_EDGE |
530 * DMA_CFG_TRIGBURST_BURST | DMA_CFG_BURSTPOWER_8 |
531 * DMA_CFG_CHPRIORITY(3)));<br>
532 *
533 * For non-peripheral DMA triggering (DMA_CFG_HWTRIGEN definition), use the
534 * DMA input mux functions to configure the DMA trigger source for a DMA channel.
535 */
Chip_DMA_SetupChannelConfig(LPC_DMA_T * pDMA,DMA_CHID_T ch,uint32_t cfg)536 STATIC INLINE void Chip_DMA_SetupChannelConfig(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t cfg)
537 {
538 pDMA->DMACH[ch].CFG = cfg;
539 }
540
541 /* DMA channel control and status register definitions */
542 #define DMA_CTLSTAT_VALIDPENDING (1 << 0) /*!< Valid pending flag for this channel */
543 #define DMA_CTLSTAT_TRIG (1 << 2) /*!< Trigger flag. Indicates that the trigger for this channel is currently set */
544
545 /**
546 * @brief Returns channel specific status flags
547 * @param pDMA : The base of DMA controller on the chip
548 * @param ch : DMA channel ID
549 * @return AN Or'ed value of DMA_CTLSTAT_VALIDPENDING and DMA_CTLSTAT_TRIG
550 */
Chip_DMA_GetChannelStatus(LPC_DMA_T * pDMA,DMA_CHID_T ch)551 STATIC INLINE uint32_t Chip_DMA_GetChannelStatus(LPC_DMA_T *pDMA, DMA_CHID_T ch)
552 {
553 return pDMA->DMACH[ch].CTLSTAT;
554 }
555
556 /* DMA channel transfer configuration registers definitions */
557 #define DMA_XFERCFG_CFGVALID (1 << 0) /*!< Configuration Valid flag */
558 #define DMA_XFERCFG_RELOAD (1 << 1) /*!< Indicates whether the channels control structure will be reloaded when the current descriptor is exhausted */
559 #define DMA_XFERCFG_SWTRIG (1 << 2) /*!< Software Trigger */
560 #define DMA_XFERCFG_CLRTRIG (1 << 3) /*!< Clear Trigger */
561 #define DMA_XFERCFG_SETINTA (1 << 4) /*!< Set Interrupt flag A for this channel to fire when descriptor is complete */
562 #define DMA_XFERCFG_SETINTB (1 << 5) /*!< Set Interrupt flag B for this channel to fire when descriptor is complete */
563 #define DMA_XFERCFG_WIDTH_8 (0 << 8) /*!< 8-bit transfers are performed */
564 #define DMA_XFERCFG_WIDTH_16 (1 << 8) /*!< 16-bit transfers are performed */
565 #define DMA_XFERCFG_WIDTH_32 (2 << 8) /*!< 32-bit transfers are performed */
566 #define DMA_XFERCFG_SRCINC_0 (0 << 12) /*!< DMA source address is not incremented after a transfer */
567 #define DMA_XFERCFG_SRCINC_1 (1 << 12) /*!< DMA source address is incremented by 1 (width) after a transfer */
568 #define DMA_XFERCFG_SRCINC_2 (2 << 12) /*!< DMA source address is incremented by 2 (width) after a transfer */
569 #define DMA_XFERCFG_SRCINC_4 (3 << 12) /*!< DMA source address is incremented by 4 (width) after a transfer */
570 #define DMA_XFERCFG_DSTINC_0 (0 << 14) /*!< DMA destination address is not incremented after a transfer */
571 #define DMA_XFERCFG_DSTINC_1 (1 << 14) /*!< DMA destination address is incremented by 1 (width) after a transfer */
572 #define DMA_XFERCFG_DSTINC_2 (2 << 14) /*!< DMA destination address is incremented by 2 (width) after a transfer */
573 #define DMA_XFERCFG_DSTINC_4 (3 << 14) /*!< DMA destination address is incremented by 4 (width) after a transfer */
574 #define DMA_XFERCFG_XFERCOUNT(n) ((n - 1) << 16) /*!< DMA transfer count in 'transfers', between (0)1 and (1023)1024 */
575
576 /**
577 * @brief Setup a DMA channel transfer configuration
578 * @param pDMA : The base of DMA controller on the chip
579 * @param ch : DMA channel ID
580 * @param cfg : An Or'ed value of DMA_XFERCFG_* values that define the channel's transfer configuration
581 * @return Nothing
582 * @note This function sets up the transfer configuration for the DMA channel.<br>
583 *
584 * The following example show how to configure the channel's transfer for
585 * multiple transfer descriptors (ie, ping-pong), interrupt 'A' trigger on
586 * transfer descriptor completion, 128 byte size transfers, and source and
587 * destination address increment.<br>
588 * Example: Chip_DMA_SetupChannelTransfer(pDMA, SSP0_RX_DMA,
589 * (DMA_XFERCFG_CFGVALID | DMA_XFERCFG_RELOAD | DMA_XFERCFG_SETINTA |
590 * DMA_XFERCFG_WIDTH_8 | DMA_XFERCFG_SRCINC_1 | DMA_XFERCFG_DSTINC_1 |
591 * DMA_XFERCFG_XFERCOUNT(128)));<br>
592 */
Chip_DMA_SetupChannelTransfer(LPC_DMA_T * pDMA,DMA_CHID_T ch,uint32_t cfg)593 STATIC INLINE void Chip_DMA_SetupChannelTransfer(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t cfg)
594 {
595 pDMA->DMACH[ch].XFERCFG = cfg;
596 }
597
598 /**
599 * @brief Set DMA transfer register interrupt bits (safe)
600 * @param pDMA : The base of DMA controller on the chip
601 * @param ch : DMA channel ID
602 * @param mask : Bits to set
603 * @return Nothing
604 * @note This function safely sets bits in the DMA channel specific XFERCFG
605 * register.
606 */
607 void Chip_DMA_SetTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask);
608
609 /**
610 * @brief Clear DMA transfer register interrupt bits (safe)
611 * @param pDMA : The base of DMA controller on the chip
612 * @param ch : DMA channel ID
613 * @param mask : Bits to clear
614 * @return Nothing
615 * @note This function safely clears bits in the DMA channel specific XFERCFG
616 * register.
617 */
618 void Chip_DMA_ClearTranBits(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t mask);
619
620 /**
621 * @brief Update the transfer size in an existing DMA channel transfer configuration
622 * @param pDMA : The base of DMA controller on the chip
623 * @param ch : DMA channel ID
624 * @param trans : Number of transfers to update the transfer configuration to (1 - 1023)
625 * @return Nothing
626 */
627 void Chip_DMA_SetupChannelTransferSize(LPC_DMA_T *pDMA, DMA_CHID_T ch, uint32_t trans);
628
629 /**
630 * @brief Sets a DMA channel configuration as valid
631 * @param pDMA : The base of DMA controller on the chip
632 * @param ch : DMA channel ID
633 * @return Nothing
634 */
Chip_DMA_SetChannelValid(LPC_DMA_T * pDMA,DMA_CHID_T ch)635 STATIC INLINE void Chip_DMA_SetChannelValid(LPC_DMA_T *pDMA, DMA_CHID_T ch)
636 {
637 Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_CFGVALID);
638 }
639
640 /**
641 * @brief Sets a DMA channel configuration as invalid
642 * @param pDMA : The base of DMA controller on the chip
643 * @param ch : DMA channel ID
644 * @return Nothing
645 */
Chip_DMA_SetChannelInValid(LPC_DMA_T * pDMA,DMA_CHID_T ch)646 STATIC INLINE void Chip_DMA_SetChannelInValid(LPC_DMA_T *pDMA, DMA_CHID_T ch)
647 {
648 Chip_DMA_ClearTranBits(pDMA, ch, DMA_XFERCFG_CFGVALID);
649 }
650
651 /**
652 * @brief Performs a software trigger of the DMA channel
653 * @param pDMA : The base of DMA controller on the chip
654 * @param ch : DMA channel ID
655 * @return Nothing
656 */
Chip_DMA_SWTriggerChannel(LPC_DMA_T * pDMA,DMA_CHID_T ch)657 STATIC INLINE void Chip_DMA_SWTriggerChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch)
658 {
659 Chip_DMA_SetTranBits(pDMA, ch, DMA_XFERCFG_SWTRIG);
660 }
661
662 /**
663 * @brief Sets up a DMA channel with the passed DMA transfer descriptor
664 * @param pDMA : The base of DMA controller on the chip
665 * @param ch : DMA channel ID
666 * @param desc : Pointer to DMA transfer descriptor
667 * @return false if the DMA channel was active, otherwise true
668 * @note This function will set the DMA descriptor in the SRAM table to the
669 * the passed descriptor. This function is only meant to be used when
670 * the DMA channel is not active and can be used to setup the
671 * initial transfer for a linked list or ping-pong buffer or just a
672 * single transfer without a next descriptor.<br>
673 *
674 * If using this function to write the initial transfer descriptor in
675 * a linked list or ping-pong buffer configuration, it should contain a
676 * non-NULL 'next' field pointer.
677 */
678 bool Chip_DMA_SetupTranChannel(LPC_DMA_T *pDMA, DMA_CHID_T ch, DMA_CHDESC_T *desc);
679
680 /**
681 * @}
682 */
683
684 /**
685 * @}
686 */
687
688 #ifdef __cplusplus
689 }
690 #endif
691
692 #endif /* __DMA_15XX_H_ */
693