1 /*
2 * @brief LPC15xx SPI driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2014
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SPI_15XX_H_
33 #define __SPI_15XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /** @defgroup SPI_15XX CHIP: LPC15xx SPI driver
40 * @ingroup CHIP_15XX_Drivers
41 * @{
42 */
43 /**
44 * @brief SPI register block structure
45 */
46 typedef struct { /*!< SPI Structure */
47 __IO uint32_t CFG; /*!< SPI Configuration register*/
48 __IO uint32_t DLY; /*!< SPI Delay register*/
49 __IO uint32_t STAT; /*!< SPI Status. register*/
50 __IO uint32_t INTENSET; /*!< SPI Interrupt Enable.Set register*/
51 __O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. register*/
52 __I uint32_t RXDAT; /*!< SPI Receive Data register*/
53 __IO uint32_t TXDATCTL; /*!< SPI Transmit Data with Control register*/
54 __IO uint32_t TXDAT; /*!< SPI Transmit Data register*/
55 __IO uint32_t TXCTRL; /*!< SPI Transmit Control register*/
56 __IO uint32_t DIV; /*!< SPI clock Divider register*/
57 __I uint32_t INTSTAT; /*!< SPI Interrupt Status register*/
58 } LPC_SPI_T;
59
60 /**
61 * Macro defines for SPI Configuration register
62 */
63 /* SPI CFG Register BitMask */
64 #define SPI_CFG_BITMASK ((uint32_t) 0xFBD)
65 /** SPI enable */
66 #define SPI_CFG_SPI_EN ((uint32_t) (1 << 0))
67 /** SPI Slave Mode Select */
68 #define SPI_CFG_SLAVE_EN ((uint32_t) (0 << 2))
69 /** SPI Master Mode Select */
70 #define SPI_CFG_MASTER_EN ((uint32_t) (1 << 2))
71 /** SPI MSB First mode enable */
72 #define SPI_CFG_MSB_FIRST_EN ((uint32_t) (0 << 3)) /*Data will be transmitted and received in standard order (MSB first).*/
73 /** SPI LSB First mode enable */
74 #define SPI_CFG_LSB_FIRST_EN ((uint32_t) (1 << 3))/*Data will be transmitted and received in reverse order (LSB first).*/
75 /** SPI Clock Phase Select*/
76 #define SPI_CFG_CPHA_FIRST ((uint32_t) (0 << 4)) /*Capture data on the first edge, Change data on the following edge*/
77 #define SPI_CFG_CPHA_SECOND ((uint32_t) (1 << 4)) /*Change data on the first edge, Capture data on the following edge*/
78 /** SPI Clock Polarity Select*/
79 #define SPI_CFG_CPOL_LO ((uint32_t) (0 << 5)) /* The rest state of the clock (between frames) is low.*/
80 #define SPI_CFG_CPOL_HI ((uint32_t) (1 << 5)) /* The rest state of the clock (between frames) is high.*/
81 /** SPI control 1 loopback mode enable */
82 #define SPI_CFG_LBM_EN ((uint32_t) (1 << 7))
83 /** SPI SSEL0 Polarity Select*/
84 #define SPI_CFG_SPOL0_LO ((uint32_t) (0 << 8)) /* SSEL0 is active Low */
85 #define SPI_CFG_SPOL0_HI ((uint32_t) (1 << 8)) /* SSEL0 is active High */
86 /** SPI SSEL1 Polarity Select*/
87 #define SPI_CFG_SPOL1_LO ((uint32_t) (0 << 9)) /* SSEL1 is active Low */
88 #define SPI_CFG_SPOL1_HI ((uint32_t) (1 << 9)) /* SSEL1 is active High */
89 /** SPI SSEL2 Polarity Select*/
90 /** Note that SSEL2, SSEL3 is only available on SPI0 not on SPI1 */
91 #define SPI_CFG_SPOL2_LO ((uint32_t) (0 << 10)) /* SSEL2 is active Low */
92 #define SPI_CFG_SPOL2_HI ((uint32_t) (1 << 10)) /* SSEL2 is active High */
93 /** SPI SSEL3 Polarity Select*/
94 #define SPI_CFG_SPOL3_LO ((uint32_t) (0 << 11)) /* SSEL3 is active Low */
95 #define SPI_CFG_SPOL3_HI ((uint32_t) (1 << 11)) /* SSEL3 is active High */
96
97 /**
98 * Macro defines for SPI Delay register
99 */
100 /** SPI DLY Register Mask */
101 #define SPI_DLY_BITMASK ((uint32_t) 0xFFFF)
102 /** Controls the amount of time between SSEL assertion and the beginning of a data frame. */
103 #define SPI_DLY_PRE_DELAY(n) ((uint32_t) ((n) & 0x0F)) /* Time Unit: SPI clock time */
104 /** Controls the amount of time between the end of a data frame and SSEL deassertion. */
105 #define SPI_DLY_POST_DELAY(n) ((uint32_t) (((n) & 0x0F) << 4)) /* Time Unit: SPI clock time */
106 /** Controls the minimum amount of time between adjacent data frames. */
107 #define SPI_DLY_FRAME_DELAY(n) ((uint32_t) (((n) & 0x0F) << 8)) /* Time Unit: SPI clock time */
108 /** Controls the minimum amount of time that the SSEL is deasserted between transfers. */
109 #define SPI_DLY_TRANSFER_DELAY(n) ((uint32_t) (((n) & 0x0F) << 12)) /* Time Unit: SPI clock time */
110
111 /**
112 * Macro defines for SPI Status register
113 */
114 /* SPI STAT Register BitMask */
115 #define SPI_STAT_BITMASK ((uint32_t) 0x1FF)
116 /* Receiver Ready Flag */
117 #define SPI_STAT_RXRDY ((uint32_t) (1 << 0)) /* Data is ready for read */
118 /* Transmitter Ready Flag */
119 #define SPI_STAT_TXRDY ((uint32_t) (1 << 1)) /* Data may be written to transmit buffer */
120 /* Receiver Overrun interrupt flag */
121 #define SPI_STAT_RXOV ((uint32_t) (1 << 2)) /* Data comes while receiver buffer is in used */
122 /* Transmitter Underrun interrupt flag (In Slave Mode only) */
123 #define SPI_STAT_TXUR ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */
124 /* Slave Select Assert */
125 #define SPI_STAT_SSA ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */
126 /* Slave Select Deassert */
127 #define SPI_STAT_SSD ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */
128 /* Stalled status flag */
129 #define SPI_STAT_STALLED ((uint32_t) (1 << 6)) /* SPI is currently in a stall condition. */
130 /* End Transfer flag. */
131 #define SPI_STAT_EOT ((uint32_t) (1 << 7)) /* The current frame is the last frame of the current transfer. */
132 /* Master Idle status flag. */
133 #define SPI_STAT_MSTIDLE ((uint32_t) (1 << 8)) /* SPI master function is fully idle. */
134
135 /* Clear RXOV Flag */
136 #define SPI_STAT_CLR_RXOV ((uint32_t) (1 << 2))
137 /* Clear TXUR Flag */
138 #define SPI_STAT_CLR_TXUR ((uint32_t) (1 << 3))
139 /* Clear SSA Flag */
140 #define SPI_STAT_CLR_SSA ((uint32_t) (1 << 4))
141 /* Clear SSD Flag */
142 #define SPI_STAT_CLR_SSD ((uint32_t) (1 << 5))
143 /*Force an end to the current transfer */
144 #define SPI_STAT_FORCE_EOT ((uint32_t) (1 << 7))
145
146 /**
147 * Macro defines for SPI Interrupt Enable read and Set register
148 */
149 /* SPI INTENSET Register BitMask */
150 #define SPI_INTENSET_BITMASK ((uint32_t) 0x3F)
151 /** Enable Interrupt when receiver data is available */
152 #define SPI_INTENSET_RXRDYEN ((uint32_t) (1 << 0))
153 /** Enable Interrupt when the transmitter holding register is available. */
154 #define SPI_INTENSET_TXRDYEN ((uint32_t) (1 << 1))
155 /** Enable Interrupt when a receiver overrun occurs */
156 #define SPI_INTENSET_RXOVEN ((uint32_t) (1 << 2))
157 /** Enable Interrupt when a transmitter underrun occurs (In Slave Mode Only)*/
158 #define SPI_INTENSET_TXUREN ((uint32_t) (1 << 3))
159 /** Enable Interrupt when the Slave Select is asserted.*/
160 #define SPI_INTENSET_SSAEN ((uint32_t) (1 << 4))
161 /** Enable Interrupt when the Slave Select is deasserted..*/
162 #define SPI_INTENSET_SSDEN ((uint32_t) (1 << 5))
163
164 /**
165 * Macro defines for SPI Interrupt Enable Clear register
166 */
167 /* SPI INTENCLR Register BitMask */
168 #define SPI_INTENCLR_BITMASK ((uint32_t) 0x3F)
169 /** Disable Interrupt when receiver data is available */
170 #define SPI_INTENCLR_RXRDYEN ((uint32_t) (1 << 0))
171 /** Disable Interrupt when the transmitter holding register is available. */
172 #define SPI_INTENCLR_TXRDYEN ((uint32_t) (1 << 1))
173 /** Disable Interrupt when a receiver overrun occurs */
174 #define SPI_INTENCLR_RXOVEN ((uint32_t) (1 << 2))
175 /** Disable Interrupt when a transmitter underrun occurs (In Slave Mode Only)*/
176 #define SPI_INTENCLR_TXUREN ((uint32_t) (1 << 3))
177 /** Disable Interrupt when the Slave Select is asserted.*/
178 #define SPI_INTENCLR_SSAEN ((uint32_t) (1 << 4))
179 /** Disable Interrupt when the Slave Select is deasserted..*/
180 #define SPI_INTENCLR_SSDEN ((uint32_t) (1 << 5))
181
182 /**
183 * Macro defines for SPI Receiver Data register
184 */
185 /* SPI RXDAT Register BitMask */
186 #define SPI_RXDAT_BITMASK ((uint32_t) 0x1FFFFF)
187 /** Receiver Data */
188 #define SPI_RXDAT_DATA(n) ((uint32_t) ((n) & 0xFFFF))
189 /** The state of SSEL0 pin */
190 #define SPI_RXDAT_RXSSEL0_ACTIVE ((uint32_t) (0 << 16)) /* SSEL0 is in active state */
191 #define SPI_RXDAT_RXSSEL0_INACTIVE ((uint32_t) (1 << 16)) /* SSEL0 is in inactive state */
192 #define SPI_RXDAT_RXSSEL0_FLAG ((uint32_t) (1 << 16)) /* SSEL0 Rx Flag */
193 /** The state of SSEL1 pin */
194 #define SPI_RXDAT_RXSSEL1_ACTIVE ((uint32_t) (0 << 17)) /* SSEL1 is in active state */
195 #define SPI_RXDAT_RXSSEL1_INACTIVE ((uint32_t) (1 << 17)) /* SSEL1 is in inactive state */
196 #define SPI_RXDAT_RXSSEL1_FLAG ((uint32_t) (1 << 17)) /* SSEL1 Rx Flag */
197 /** The state of SSEL2 pin */
198 #define SPI_RXDAT_RXSSEL2_ACTIVE ((uint32_t) (0 << 18)) /* SSEL2 is in active state */
199 #define SPI_RXDAT_RXSSEL2_INACTIVE ((uint32_t) (1 << 18)) /* SSEL2 is in inactive state */
200 #define SPI_RXDAT_RXSSEL2_FLAG ((uint32_t) (1 << 18)) /* SSEL2 Rx Flag */
201 /** The state of SSEL3 pin */
202 #define SPI_RXDAT_RXSSEL3_ACTIVE ((uint32_t) (0 << 19)) /* SSEL3 is in active state */
203 #define SPI_RXDAT_RXSSEL3_INACTIVE ((uint32_t) (1 << 19)) /* SSEL3 is in inactive state */
204 #define SPI_RXDAT_RXSSEL3_FLAG ((uint32_t) (1 << 19)) /* SSEL3 Rx Flag */
205 /** Start of Transfer flag */
206 #define SPI_RXDAT_SOT ((uint32_t) (1 << 20)) /* This is the first frame received after SSEL is asserted */
207
208 /**
209 * Macro defines for SPI Transmitter Data and Control register
210 */
211 /* SPI TXDATCTL Register BitMask */
212 #define SPI_TXDATCTL_BITMASK ((uint32_t) 0xF7FFFFF)
213 /* SPI Transmit Data */
214 #define SPI_TXDATCTL_DATA(n) ((uint32_t) ((n) & 0xFFFF))
215 /*Assert/Deassert SSEL0 pin*/
216 #define SPI_TXDATCTL_ASSERT_SSEL0 ((uint32_t) (0 << 16))
217 #define SPI_TXDATCTL_DEASSERT_SSEL0 ((uint32_t) (1 << 16))
218 /*Assert/Deassert SSEL1 pin*/
219 #define SPI_TXDATCTL_ASSERT_SSEL1 ((uint32_t) (0 << 17))
220 #define SPI_TXDATCTL_DEASSERT_SSEL1 ((uint32_t) (1 << 17))
221 /*Assert/Deassert SSEL2 pin*/
222 /** Note that SSEL2, SSEL3 is only available on SPI0 not on SPI1 */
223 #define SPI_TXDATCTL_ASSERT_SSEL2 ((uint32_t) (0 << 18))
224 #define SPI_TXDATCTL_DEASSERT_SSEL2 ((uint32_t) (1 << 18))
225 /*Assert/Deassert SSEL3 pin*/
226 #define SPI_TXDATCTL_ASSERT_SSEL3 ((uint32_t) (0 << 19))
227 #define SPI_TXDATCTL_DEASSERT_SSEL3 ((uint32_t) (1 << 19))
228 /* Mask for Slave Select bits */
229 #define SPI_TXDATCTL_SSEL_MASK ((uint32_t) (0x0F0000))
230
231 /** End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame) */
232 #define SPI_TXDATCTL_EOT ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */
233 /** End of Frame flag (FRAME_DELAY is applied after sending the current part) */
234 #define SPI_TXDATCTL_EOF ((uint32_t) (1 << 21)) /* This is the last part of the current frame */
235 /** Receive Ignore Flag */
236 #define SPI_TXDATCTL_RXIGNORE ((uint32_t) (1 << 22)) /* Received data is ignored */
237 /** Transmit Data Length */
238 #define SPI_TXDATCTL_LEN(n) ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */
239
240 /**
241 * Macro defines for SPI Transmitter Data Register
242 */
243 /* SPI Transmit Data */
244 #define SPI_TXDAT_DATA(n) ((uint32_t) ((n) & 0xFFFF))
245
246 /**
247 * Macro defines for SPI Transmitter Control register
248 */
249 /* SPI TXDATCTL Register BitMask */
250 #define SPI_TXCTL_BITMASK ((uint32_t) 0xF7F0000)
251 /*Assert/Deassert SSEL0 pin*/
252 #define SPI_TXCTL_ASSERT_SSEL0 ((uint32_t) (0 << 16))
253 #define SPI_TXCTL_DEASSERT_SSEL0 ((uint32_t) (1 << 16))
254 /*Assert/Deassert SSEL1 pin*/
255 #define SPI_TXCTL_ASSERT_SSEL1 ((uint32_t) (0 << 17))
256 #define SPI_TXCTL_DEASSERT_SSEL1 ((uint32_t) (1 << 17))
257 /*Assert/Deassert SSEL2 pin*/
258 /** Note that SSEL2, SSEL3 is only available on SPI0 not on SPI1 */
259 #define SPI_TXCTL_ASSERT_SSEL2 ((uint32_t) (0 << 18))
260 #define SPI_TXCTL_DEASSERT_SSEL2 ((uint32_t) (1 << 18))
261 /*Assert/Deassert SSEL3 pin*/
262 #define SPI_TXCTL_ASSERT_SSEL3 ((uint32_t) (0 << 19))
263 #define SPI_TXCTL_DEASSERT_SSEL3 ((uint32_t) (1 << 19))
264 /** End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame) */
265 #define SPI_TXCTL_EOT ((uint32_t) (1 << 20)) /* This is the last frame of the current transfer */
266 /** End of Frame flag (FRAME_DELAY is applied after sending the current part) */
267 #define SPI_TXCTL_EOF ((uint32_t) (1 << 21)) /* This is the last part of the current frame */
268 /** Receive Ignore Flag */
269 #define SPI_TXCTL_RXIGNORE ((uint32_t) (1 << 22)) /* Received data is ignored */
270 /** Transmit Data Length */
271 #define SPI_TXCTL_LEN(n) ((uint32_t) (((n) & 0x0F) << 24)) /* Frame Length -1 */
272
273 /**
274 * Macro defines for SPI Divider register
275 */
276 /** Rate divider value (In Master Mode only)*/
277 #define SPI_DIV_VAL(n) ((uint32_t) ((n) & 0xFFFF)) /* SPI_CLK = PCLK/(DIV_VAL+1)*/
278
279 /**
280 * Macro defines for SPI Interrupt Status register
281 */
282 /* SPI INTSTAT Register Bitmask */
283 #define SPI_INTSTAT_BITMASK ((uint32_t) 0x3F)
284 /* Receiver Ready Flag */
285 #define SPI_INTSTAT_RXRDY ((uint32_t) (1 << 0)) /* Data is ready for read */
286 /* Transmitter Ready Flag */
287 #define SPI_INTSTAT_TXRDY ((uint32_t) (1 << 1)) /* Data may be written to transmit buffer */
288 /* Receiver Overrun interrupt flag */
289 #define SPI_INTSTAT_RXOV ((uint32_t) (1 << 2)) /* Data comes while receiver buffer is in used */
290 /* Transmitter Underrun interrupt flag (In Slave Mode only) */
291 #define SPI_INTSTAT_TXUR ((uint32_t) (1 << 3)) /* There is no data to be sent in the next input clock */
292 /* Slave Select Assert */
293 #define SPI_INTSTAT_SSA ((uint32_t) (1 << 4)) /* There is SSEL transition from deasserted to asserted */
294 /* Slave Select Deassert */
295 #define SPI_INTSTAT_SSD ((uint32_t) (1 << 5)) /* There is SSEL transition from asserted to deasserted */
296
297 /** @brief SPI Mode*/
298 typedef enum {
299 SPI_MODE_MASTER = SPI_CFG_MASTER_EN, /* Master Mode */
300 SPI_MODE_SLAVE = SPI_CFG_SLAVE_EN /* Slave Mode */
301 } SPI_MODE_T;
302
303 /** @brief SPI Clock Mode*/
304 typedef enum IP_SPI_CLOCK_MODE {
305 SPI_CLOCK_CPHA0_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_FIRST, /**< CPHA = 0, CPOL = 0 */
306 SPI_CLOCK_CPHA0_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_FIRST, /**< CPHA = 0, CPOL = 1 */
307 SPI_CLOCK_CPHA1_CPOL0 = SPI_CFG_CPOL_LO | SPI_CFG_CPHA_SECOND, /**< CPHA = 1, CPOL = 0 */
308 SPI_CLOCK_CPHA1_CPOL1 = SPI_CFG_CPOL_HI | SPI_CFG_CPHA_SECOND, /**< CPHA = 1, CPOL = 1 */
309 SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0,/**< alias */
310 SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0,/**< alias */
311 SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1,/**< alias */
312 SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1,/**< alias */
313 } SPI_CLOCK_MODE_T;
314
315 /** @brief SPI Data Order Mode*/
316 typedef enum IP_SPI_DATA_ORDER {
317 SPI_DATA_MSB_FIRST = SPI_CFG_MSB_FIRST_EN, /* Standard Order */
318 SPI_DATA_LSB_FIRST = SPI_CFG_LSB_FIRST_EN, /* Reverse Order */
319 } SPI_DATA_ORDER_T;
320
321 /**
322 * @brief SPI Configure Struct
323 */
324 typedef struct {
325 SPI_MODE_T Mode; /* Mode Select */
326 SPI_CLOCK_MODE_T ClockMode; /* CPHA CPOL Select */
327 SPI_DATA_ORDER_T DataOrder; /* MSB/LSB First */
328 uint32_t SSELPol; /* SSEL Polarity Select */
329 uint16_t ClkDiv; /* SPI Clock Divider Value */
330 } SPI_CFG_T;
331
332 /**
333 * @brief SPI Delay Configure Struct
334 */
335 typedef struct {
336 uint8_t PreDelay; /* Pre-delay value in SPI clock time */
337 uint8_t PostDelay; /* Post-delay value in SPI clock time */
338 uint8_t FrameDelay; /* Delay value between frames of a transfer in SPI clock time */
339 uint8_t TransferDelay; /* Delay value between transfers in SPI clock time */
340 } SPI_DELAY_CONFIG_T;
341
342 /**
343 * @brief SPI data setup structure
344 */
345 typedef struct {
346 uint16_t *pTx; /**< Pointer to data buffer*/
347 uint32_t TxCnt;/* Transmit Counter */
348 uint16_t *pRx; /**< Pointer to data buffer*/
349 uint32_t RxCnt;/* Transmit Counter */
350 uint32_t Length; /**< Data Length*/
351 uint32_t ssel; /**< Slave select bits */
352 uint16_t DataSize; /** < The size of a frame (1-16)*/
353 } SPI_DATA_SETUP_T;
354
355 /**
356 * @brief Set the SPI Config register
357 * @param pSPI : The base SPI peripheral on the chip
358 * @param pConfig : SPI Configuration
359 * @return Nothing
360 */
361 void Chip_SPI_SetConfig(LPC_SPI_T *pSPI, SPI_CFG_T *pConfig);
362
363 /**
364 * @brief Calculate the divider for SPI clock
365 * @param pSPI : The base of SPI peripheral on the chip
366 * @param bitRate : Expected clock rate
367 * @return Divider value
368 */
369 uint32_t Chip_SPI_CalClkRateDivider(LPC_SPI_T *pSPI, uint32_t bitRate);
370
371 /**
372 * @brief Config SPI Delay parameters
373 * @param pSPI : The base of SPI peripheral on the chip
374 * @param pConfig : SPI Delay Configure Struct
375 * @return Nothing
376 * @note The SPI delays are setup
377 */
378 void Chip_SPI_DelayConfig(LPC_SPI_T *pSPI, SPI_DELAY_CONFIG_T *pConfig);
379
380 /**
381 * @brief SPI Initialization
382 * @param pSPI : The base SPI peripheral on the chip
383 * @return Nothing
384 */
385 void Chip_SPI_Init(LPC_SPI_T *pSPI);
386
387 /**
388 * @brief Disable SPI operation
389 * @param pSPI : The base of SPI peripheral on the chip
390 * @return Nothing
391 * @note The SPI controller is disabled
392 */
393 void Chip_SPI_DeInit(LPC_SPI_T *pSPI);
394
395 /**
396 * @brief Enable/Disable SPI interrupt
397 * @param pSPI : The base SPI peripheral on the chip
398 * @param IntMask : Interrupt mask
399 * @param NewState : ENABLE or DISABLE interrupt
400 * @return Nothing
401 */
402 void Chip_SPI_Int_Cmd(LPC_SPI_T *pSPI, uint32_t IntMask, FunctionalState NewState);
403
404 /**
405 * @brief Enable SPI peripheral
406 * @param pSPI : The base of SPI peripheral on the chip
407 * @return Nothing
408 */
Chip_SPI_Enable(LPC_SPI_T * pSPI)409 STATIC INLINE void Chip_SPI_Enable(LPC_SPI_T *pSPI)
410 {
411 pSPI->CFG |= SPI_CFG_SPI_EN;
412 }
413
414 /**
415 * @brief Disable SPI peripheral
416 * @param pSPI : The base of SPI peripheral on the chip
417 * @return Nothing
418 */
Chip_SPI_Disable(LPC_SPI_T * pSPI)419 STATIC INLINE void Chip_SPI_Disable(LPC_SPI_T *pSPI)
420 {
421 pSPI->CFG &= (~SPI_CFG_SPI_EN) & SPI_CFG_BITMASK;
422 }
423
424 /**
425 * @brief Enable loopback mode
426 * @param pSPI : The base of SPI peripheral on the chip
427 * @return Nothing
428 * @note Serial input is taken from the serial output (MOSI or MISO) rather
429 * than the serial input pin
430 */
Chip_SPI_EnableLoopBack(LPC_SPI_T * pSPI)431 STATIC INLINE void Chip_SPI_EnableLoopBack(LPC_SPI_T *pSPI)
432 {
433 pSPI->CFG |= SPI_CFG_LBM_EN;
434 }
435
436 /**
437 * @brief Disable loopback mode
438 * @param pSPI : The base of SPI peripheral on the chip
439 * @return Nothing
440 * @note Serial input is taken from the serial input pin
441 */
Chip_SPI_DisableLoopBack(LPC_SPI_T * pSPI)442 STATIC INLINE void Chip_SPI_DisableLoopBack(LPC_SPI_T *pSPI)
443 {
444 pSPI->CFG &= (~SPI_CFG_LBM_EN) & SPI_CFG_BITMASK;
445 }
446
447 /**
448 * @brief Get the current status of SPI controller
449 * @param pSPI : The base of SPI peripheral on the chip
450 * @return SPI Status (Or-ed bit value of SPI_STAT_*)
451 */
Chip_SPI_GetStatus(LPC_SPI_T * pSPI)452 STATIC INLINE uint32_t Chip_SPI_GetStatus(LPC_SPI_T *pSPI)
453 {
454 return pSPI->STAT;
455 }
456
457 /**
458 * @brief Clear SPI status
459 * @param pSPI : The base of SPI peripheral on the chip
460 * @param Flag : Clear Flag (Or-ed bit value of SPI_STAT_CLR_*)
461 * @return Nothing
462 */
Chip_SPI_ClearStatus(LPC_SPI_T * pSPI,uint32_t Flag)463 STATIC INLINE void Chip_SPI_ClearStatus(LPC_SPI_T *pSPI, uint32_t Flag)
464 {
465 pSPI->STAT = (Flag & SPI_STAT_BITMASK);
466 }
467
468 /**
469 * @brief Set control information including SSEL, EOT, EOF RXIGNORE and FLEN
470 * @param pSPI : The base of SPI peripheral on the chip
471 * @param len : Data size (1-16)
472 * @param Flag : Flag control (Or-ed values of SPI_TXCTL_*)
473 * @note The control information has no effect unless data is later written to TXDAT
474 * @return Nothing
475 */
Chip_SPI_SetControlInfo(LPC_SPI_T * pSPI,uint8_t len,uint32_t Flag)476 STATIC INLINE void Chip_SPI_SetControlInfo(LPC_SPI_T *pSPI, uint8_t len, uint32_t Flag)
477 {
478 pSPI->TXCTRL = (Flag & SPI_TXCTL_BITMASK) | SPI_TXDATCTL_LEN(len - 1);
479 }
480
481 /**
482 * @brief Send the first Frame of a transfer (Rx Ignore)
483 * @param pSPI : The base of SPI peripheral on the chip
484 * @param Data : Transmit data
485 * @param DataSize : Data Size (1-16)
486 * @param ssel : ORed value of Slave Select bits
487 * @return Nothing
488 */
Chip_SPI_SendFirstFrame_RxIgnore(LPC_SPI_T * pSPI,uint16_t Data,uint8_t DataSize,uint32_t ssel)489 STATIC INLINE void Chip_SPI_SendFirstFrame_RxIgnore(LPC_SPI_T *pSPI, uint16_t Data, uint8_t DataSize, uint32_t ssel)
490 {
491 pSPI->TXDATCTL = (ssel & SPI_TXDATCTL_SSEL_MASK) | SPI_TXDATCTL_EOF | SPI_TXDATCTL_RXIGNORE | SPI_TXDATCTL_LEN(
492 DataSize - 1) | SPI_TXDATCTL_DATA(Data);
493 }
494
495 /**
496 * @brief Send the first Frame of a transfer
497 * @param pSPI : The base of SPI peripheral on the chip
498 * @param Data : Transmit data
499 * @param DataSize : Data Size (1-16)
500 * @param ssel : ORed value of Slave Select bits
501 * @return Nothing
502 */
Chip_SPI_SendFirstFrame(LPC_SPI_T * pSPI,uint16_t Data,uint8_t DataSize,uint32_t ssel)503 STATIC INLINE void Chip_SPI_SendFirstFrame(LPC_SPI_T *pSPI, uint16_t Data, uint8_t DataSize, uint32_t ssel)
504 {
505 pSPI->TXDATCTL =
506 (ssel & SPI_TXDATCTL_SSEL_MASK) | SPI_TXDATCTL_EOF | SPI_TXDATCTL_LEN(DataSize - 1) | SPI_TXDATCTL_DATA(Data);
507 }
508
509 /**
510 * @brief Send the middle Frame of a transfer
511 * @param pSPI : The base of SPI peripheral on the chip
512 * @param Data : Transmit data
513 * @return Nothing
514 */
Chip_SPI_SendMidFrame(LPC_SPI_T * pSPI,uint16_t Data)515 STATIC INLINE void Chip_SPI_SendMidFrame(LPC_SPI_T *pSPI, uint16_t Data)
516 {
517 pSPI->TXDAT = SPI_TXDAT_DATA(Data);
518 }
519
520 /**
521 * @brief Send the last Frame of a transfer (Rx Ignore)
522 * @param pSPI : The base of SPI peripheral on the chip
523 * @param Data : Transmit data
524 * @param DataSize : Data Size (1-16)
525 * @param ssel : ORed value of Slave Select bits
526 * @return Nothing
527 */
Chip_SPI_SendLastFrame_RxIgnore(LPC_SPI_T * pSPI,uint16_t Data,uint8_t DataSize,uint32_t ssel)528 STATIC INLINE void Chip_SPI_SendLastFrame_RxIgnore(LPC_SPI_T *pSPI, uint16_t Data, uint8_t DataSize, uint32_t ssel)
529 {
530 pSPI->TXDATCTL = (ssel & SPI_TXDATCTL_SSEL_MASK) | SPI_TXDATCTL_EOF | SPI_TXDATCTL_EOT | SPI_TXDATCTL_RXIGNORE |
531 SPI_TXDATCTL_LEN(DataSize - 1) | SPI_TXDATCTL_DATA(Data);
532 }
533
534 /**
535 * @brief Send the last Frame of a transfer
536 * @param pSPI : The base of SPI peripheral on the chip
537 * @param Data : Transmit data
538 * @param DataSize : Data Size (1-16)
539 * @param ssel : ORed value of Slave Select bits
540 * @return Nothing
541 */
Chip_SPI_SendLastFrame(LPC_SPI_T * pSPI,uint16_t Data,uint8_t DataSize,uint32_t ssel)542 STATIC INLINE void Chip_SPI_SendLastFrame(LPC_SPI_T *pSPI, uint16_t Data, uint8_t DataSize, uint32_t ssel)
543 {
544 pSPI->TXDATCTL = (ssel & SPI_TXDATCTL_SSEL_MASK) | SPI_TXDATCTL_EOF | SPI_TXDATCTL_EOT |
545 SPI_TXDATCTL_LEN(DataSize - 1) | SPI_TXDATCTL_DATA(Data);
546 }
547
548 /**
549 * @brief Read data received
550 * @param pSPI : The base of SPI peripheral on the chip
551 * @return Receive data
552 */
Chip_SPI_ReceiveFrame(LPC_SPI_T * pSPI)553 STATIC INLINE uint16_t Chip_SPI_ReceiveFrame(LPC_SPI_T *pSPI)
554 {
555 return SPI_RXDAT_DATA(pSPI->RXDAT);
556 }
557
558 /**
559 * @brief Read and return Rx Slave Select and Start of transfer flags
560 * @param pSPI : The base of SPI peripheral on the chip
561 * @return Rx Slave Select and Start of transfer flags
562 */
Chip_SPI_GetReceiveInfo(LPC_SPI_T * pSPI)563 STATIC INLINE uint16_t Chip_SPI_GetReceiveInfo(LPC_SPI_T *pSPI)
564 {
565 return pSPI->RXDAT &
566 (SPI_RXDAT_RXSSEL0_FLAG | SPI_RXDAT_RXSSEL0_FLAG | SPI_RXDAT_RXSSEL0_FLAG | SPI_RXDAT_RXSSEL0_FLAG |
567 SPI_RXDAT_SOT);
568 }
569
570 /**
571 * @brief Get the current Interrupt status of SPI controller
572 * @param pSPI : The base of SPI peripheral on the chip
573 * @return SPI Interrupt Status (Or-ed bit value of SPI_INTSTAT_*)
574 */
Chip_SPI_GetIntStatus(LPC_SPI_T * pSPI)575 STATIC INLINE uint32_t Chip_SPI_GetIntStatus(LPC_SPI_T *pSPI)
576 {
577 return pSPI->INTSTAT;
578 }
579
580 /**
581 * @brief SPI Interrupt Read/Write
582 * @param pSPI : The base SPI peripheral on the chip
583 * @param xf_setup : Pointer to a SPI_DATA_SETUP_T structure that contains specified
584 * information about transmit/receive data configuration
585 * @return SUCCESS or ERROR
586 */
587 Status Chip_SPI_Int_RWFrames(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *xf_setup);
588
589 /**
590 * @brief SPI Polling Read/Write in blocking mode
591 * @param pSPI : The base SPI peripheral on the chip
592 * @param pXfSetup : Pointer to a SPI_DATA_SETUP_T structure that contains specified
593 * information about transmit/receive data configuration
594 * @return Actual data length has been transferred
595 * @note
596 * This function can be used in both master and slave mode. It starts with writing phase and after that,
597 * a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared
598 * through xf_setup param.
599 */
600 uint32_t Chip_SPI_RWFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup);
601
602 /**
603 * @brief SPI Polling Write in blocking mode
604 * @param pSPI : The base SPI peripheral on the chip
605 * @param pXfSetup :Pointer to a SPI_DATA_SETUP_T structure that contains specified
606 * information about transmit/receive data configuration
607 * @return Actual data length has been transferred
608 * @note
609 * This function can be used in both master and slave mode. First, a writing operation will send
610 * the needed data. After that, a dummy reading operation is generated to clear data buffer
611 */
612 uint32_t Chip_SPI_WriteFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup);
613
614 /**
615 * @brief SPI Polling Read in blocking mode
616 * @param pSPI : The base SPI peripheral on the chip
617 * @param pXfSetup :Pointer to a SPI_DATA_SETUP_T structure that contains specified
618 * information about transmit/receive data configuration
619 * @return Actual data length has been read
620 * @note
621 * This function can be used in both master and slave mode. First, a writing operation will send
622 * the needed data. After that, a dummy reading operation is generated to clear data buffer
623 */
624 uint32_t Chip_SPI_ReadFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup);
625
626 /**
627 * @}
628 */
629
630 #ifdef __cplusplus
631 }
632 #endif
633
634 #endif /* __SPI_15XX_H_ */
635