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Searched refs:ENABLE (Results 1 – 25 of 116) sorted by relevance

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/external/platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/src/
A Dstm32f4xx_gpio.c127 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); in GPIO_DeInit()
132 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); in GPIO_DeInit()
137 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); in GPIO_DeInit()
142 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); in GPIO_DeInit()
147 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); in GPIO_DeInit()
152 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); in GPIO_DeInit()
157 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); in GPIO_DeInit()
162 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); in GPIO_DeInit()
168 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); in GPIO_DeInit()
173 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE); in GPIO_DeInit()
[all …]
A Dstm32f4xx_cryp_aes.c179 CRYP_Cmd(ENABLE); in CRYP_AES_ECB()
216 CRYP_Cmd(ENABLE); in CRYP_AES_ECB()
381 CRYP_Cmd(ENABLE); in CRYP_AES_CBC()
419 CRYP_Cmd(ENABLE); in CRYP_AES_CBC()
590 CRYP_Cmd(ENABLE); in CRYP_AES_CTR()
768 CRYP_Cmd(ENABLE); in CRYP_AES_GCM()
892 CRYP_Cmd(ENABLE); in CRYP_AES_GCM()
945 CRYP_Cmd(ENABLE); in CRYP_AES_GCM()
1069 CRYP_Cmd(ENABLE); in CRYP_AES_GCM()
1325 CRYP_Cmd(ENABLE); in CRYP_AES_CCM()
[all …]
A Dstm32f4xx_usart.c187 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); in USART_DeInit()
192 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); in USART_DeInit()
197 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); in USART_DeInit()
202 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); in USART_DeInit()
207 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); in USART_DeInit()
212 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); in USART_DeInit()
217 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); in USART_DeInit()
224 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); in USART_DeInit()
A Dstm32f4xx_pwr.c163 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); in PWR_DeInit()
552 *(__IO uint32_t *) CR_MRUDS_BB = (uint32_t)ENABLE; in PWR_MainRegulatorUnderDriveCmd()
576 *(__IO uint32_t *) CR_LPUDS_BB = (uint32_t)ENABLE; in PWR_LowRegulatorUnderDriveCmd()
602 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; in PWR_MainRegulatorLowVoltageCmd()
626 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; in PWR_LowRegulatorLowVoltageCmd()
A Dstm32f4xx_can.c168 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); in CAN_DeInit()
176 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); in CAN_DeInit()
184 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN3, ENABLE); in CAN_DeInit()
192 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); in CAN_DeInit()
247 if (CAN_InitStruct->CAN_TTCM == ENABLE) in CAN_Init()
257 if (CAN_InitStruct->CAN_ABOM == ENABLE) in CAN_Init()
267 if (CAN_InitStruct->CAN_AWUM == ENABLE) in CAN_Init()
277 if (CAN_InitStruct->CAN_NART == ENABLE) in CAN_Init()
287 if (CAN_InitStruct->CAN_RFLM == ENABLE) in CAN_Init()
297 if (CAN_InitStruct->CAN_TXFP == ENABLE) in CAN_Init()
[all …]
A Dstm32f4xx_wwdg.c133 RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); in WWDG_DeInit()
191 *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; in WWDG_EnableIT()
A Dstm32f4xx_rng.c96 RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE); in RNG_DeInit()
103 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_RNG, ENABLE); in RNG_DeInit()
A Dstm32f4xx_spi.c225 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); in SPI_I2S_DeInit()
232 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); in SPI_I2S_DeInit()
239 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); in SPI_I2S_DeInit()
246 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE); in SPI_I2S_DeInit()
253 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE); in SPI_I2S_DeInit()
262 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE); in SPI_I2S_DeInit()
A Dstm32f4xx_tim.c200 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); in TIM_DeInit()
205 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); in TIM_DeInit()
210 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); in TIM_DeInit()
215 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); in TIM_DeInit()
220 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); in TIM_DeInit()
225 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); in TIM_DeInit()
230 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); in TIM_DeInit()
235 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); in TIM_DeInit()
240 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); in TIM_DeInit()
245 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); in TIM_DeInit()
[all …]
/external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/src/
A Dstm32f2xx_gpio.c133 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); in GPIO_DeInit()
138 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); in GPIO_DeInit()
143 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); in GPIO_DeInit()
148 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); in GPIO_DeInit()
153 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); in GPIO_DeInit()
158 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); in GPIO_DeInit()
163 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); in GPIO_DeInit()
168 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); in GPIO_DeInit()
175 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); in GPIO_DeInit()
A Dstm32f2xx_wwdg.c142 RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); in WWDG_DeInit()
200 *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; in WWDG_EnableIT()
A Dstm32f2xx_usart.c191 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); in USART_DeInit()
196 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); in USART_DeInit()
201 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); in USART_DeInit()
206 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); in USART_DeInit()
211 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); in USART_DeInit()
218 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); in USART_DeInit()
A Dstm32f2xx_can.c176 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); in CAN_DeInit()
183 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); in CAN_DeInit()
236 if (CAN_InitStruct->CAN_TTCM == ENABLE) in CAN_Init()
246 if (CAN_InitStruct->CAN_ABOM == ENABLE) in CAN_Init()
256 if (CAN_InitStruct->CAN_AWUM == ENABLE) in CAN_Init()
266 if (CAN_InitStruct->CAN_NART == ENABLE) in CAN_Init()
276 if (CAN_InitStruct->CAN_RFLM == ENABLE) in CAN_Init()
286 if (CAN_InitStruct->CAN_TXFP == ENABLE) in CAN_Init()
412 if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) in CAN_FilterInit()
A Dstm32f2xx_tim.c207 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); in TIM_DeInit()
212 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); in TIM_DeInit()
217 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); in TIM_DeInit()
222 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); in TIM_DeInit()
227 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); in TIM_DeInit()
232 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); in TIM_DeInit()
237 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); in TIM_DeInit()
242 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); in TIM_DeInit()
247 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); in TIM_DeInit()
252 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); in TIM_DeInit()
[all …]
A Dstm32f2xx_cryp_aes.c184 CRYP_Cmd(ENABLE); in CRYP_AES_ECB()
221 CRYP_Cmd(ENABLE); in CRYP_AES_ECB()
379 CRYP_Cmd(ENABLE); in CRYP_AES_CBC()
417 CRYP_Cmd(ENABLE); in CRYP_AES_CBC()
582 CRYP_Cmd(ENABLE); in CRYP_AES_CTR()
/external/platform/stm32f1xx/STM32F10x_StdPeriph_Driver/src/
A Dstm32f10x_gpio.c114 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); in GPIO_DeInit()
119 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); in GPIO_DeInit()
124 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); in GPIO_DeInit()
129 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); in GPIO_DeInit()
134 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); in GPIO_DeInit()
139 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); in GPIO_DeInit()
146 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); in GPIO_DeInit()
160 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); in GPIO_AFIODeInit()
A Dstm32f10x_can.c122 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); in CAN_DeInit()
129 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); in CAN_DeInit()
182 if (CAN_InitStruct->CAN_TTCM == ENABLE) in CAN_Init()
192 if (CAN_InitStruct->CAN_ABOM == ENABLE) in CAN_Init()
202 if (CAN_InitStruct->CAN_AWUM == ENABLE) in CAN_Init()
212 if (CAN_InitStruct->CAN_NART == ENABLE) in CAN_Init()
222 if (CAN_InitStruct->CAN_RFLM == ENABLE) in CAN_Init()
232 if (CAN_InitStruct->CAN_TXFP == ENABLE) in CAN_Init()
356 if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) in CAN_FilterInit()
A Dstm32f10x_wwdg.c103 RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); in WWDG_DeInit()
160 *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; in WWDG_EnableIT()
A Dstm32f10x_tim.c128 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); in TIM_DeInit()
133 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); in TIM_DeInit()
138 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); in TIM_DeInit()
143 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); in TIM_DeInit()
148 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); in TIM_DeInit()
153 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); in TIM_DeInit()
158 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); in TIM_DeInit()
163 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); in TIM_DeInit()
168 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); in TIM_DeInit()
173 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); in TIM_DeInit()
[all …]
A Dstm32f10x_usart.c135 RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); in USART_DeInit()
140 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); in USART_DeInit()
145 RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); in USART_DeInit()
150 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); in USART_DeInit()
157 RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); in USART_DeInit()
/external/platform/nrfx/hal/
A Dnrf_lpcomp.h312 p_reg->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; in nrf_lpcomp_configure()
336 uint32_t lpcomp_enable_state = p_reg->ENABLE; in nrf_lpcomp_input_select()
338 p_reg->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; in nrf_lpcomp_input_select()
341 p_reg->ENABLE = lpcomp_enable_state; in nrf_lpcomp_input_select()
346 p_reg->ENABLE = LPCOMP_ENABLE_ENABLE_Enabled << LPCOMP_ENABLE_ENABLE_Pos; in nrf_lpcomp_enable()
355 p_reg->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; in nrf_lpcomp_disable()
A Dnrf_adc.h318 p_reg->ENABLE = (ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos); in nrf_adc_enable()
323 p_reg->ENABLE = (ADC_ENABLE_ENABLE_Disabled << ADC_ENABLE_ENABLE_Pos); in nrf_adc_disable()
328 return (p_reg->ENABLE == (ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos)); in nrf_adc_enable_check()
/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/CMSIS/
A Dstm32f7xx.h140 ENABLE = !DISABLE enumerator
142 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/inc/
A Dlpc_types.h68 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; enumerator
69 #define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE))
/external/platform/stm32f0xx/CMSIS/inc/
A Dstm32f0xx.h192 ENABLE = !DISABLE enumerator
194 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

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