1 //***************************************************************************** 2 // 3 // hw_epi.h - Macros for use in accessing the EPI registers. 4 // 5 // Copyright (c) 2008-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_EPI_H__ 41 #define __HW_EPI_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the External Peripheral Interface register 46 // offsets. 47 // 48 //***************************************************************************** 49 #define EPI_O_CFG 0x00000000 // EPI Configuration 50 #define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate 51 #define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration 52 #define EPI_O_GPCFG 0x00000010 // EPI General-Purpose 53 // Configuration 54 #define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration 55 #define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration 56 #define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2 57 #define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2 58 #define EPI_O_GPCFG2 0x00000014 // EPI General-Purpose 59 // Configuration 2 60 #define EPI_O_ADDRMAP 0x0000001C // EPI Address Map 61 #define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0 62 #define EPI_O_RADDR0 0x00000024 // EPI Read Address 0 63 #define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0 64 #define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1 65 #define EPI_O_RADDR1 0x00000034 // EPI Read Address 1 66 #define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1 67 #define EPI_O_STAT 0x00000060 // EPI Status 68 #define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count 69 #define EPI_O_READFIFO0 0x00000070 // EPI Read FIFO 70 #define EPI_O_READFIFO 0x00000070 // EPI Read FIFO 71 #define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1 72 #define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2 73 #define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3 74 #define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4 75 #define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5 76 #define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6 77 #define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7 78 #define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects 79 #define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count 80 #define EPI_O_IM 0x00000210 // EPI Interrupt Mask 81 #define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status 82 #define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status 83 #define EPI_O_EISC 0x0000021C // EPI Error and Interrupt Status 84 // and Clear 85 86 //***************************************************************************** 87 // 88 // The following are defines for the bit fields in the EPI_O_CFG register. 89 // 90 //***************************************************************************** 91 #define EPI_CFG_BLKEN 0x00000010 // Block Enable 92 #define EPI_CFG_MODE_M 0x0000000F // Mode Select 93 #define EPI_CFG_MODE_NONE 0x00000000 // General Purpose 94 #define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM 95 #define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8) 96 #define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16) 97 98 //***************************************************************************** 99 // 100 // The following are defines for the bit fields in the EPI_O_BAUD register. 101 // 102 //***************************************************************************** 103 #define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1 104 #define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0 105 #define EPI_BAUD_COUNT1_S 16 106 #define EPI_BAUD_COUNT0_S 0 107 108 //***************************************************************************** 109 // 110 // The following are defines for the bit fields in the EPI_O_HB16CFG register. 111 // 112 //***************************************************************************** 113 #define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable 114 #define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable 115 #define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity 116 #define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity 117 #define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait 118 #define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States 119 #define EPI_HB16CFG_WRWS_0 0x00000000 // No wait states 120 #define EPI_HB16CFG_WRWS_1 0x00000040 // 1 wait state 121 #define EPI_HB16CFG_WRWS_2 0x00000080 // 2 wait states 122 #define EPI_HB16CFG_WRWS_3 0x000000C0 // 3 wait states 123 #define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States 124 #define EPI_HB16CFG_RDWS_0 0x00000000 // No wait states 125 #define EPI_HB16CFG_RDWS_1 0x00000010 // 1 wait state 126 #define EPI_HB16CFG_RDWS_2 0x00000020 // 2 wait states 127 #define EPI_HB16CFG_RDWS_3 0x00000030 // 3 wait states 128 #define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration 129 #define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode 130 #define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0] 131 #define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0] 132 #define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0] 133 #define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0] 134 #define EPI_HB16CFG_MAXWAIT_S 8 135 136 //***************************************************************************** 137 // 138 // The following are defines for the bit fields in the EPI_O_GPCFG register. 139 // 140 //***************************************************************************** 141 #define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin 142 #define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated 143 #define EPI_GPCFG_RDYEN 0x10000000 // Ready Enable 144 #define EPI_GPCFG_FRMPIN 0x08000000 // Framing Pin 145 #define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame 146 #define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count 147 #define EPI_GPCFG_RW 0x00200000 // Read and Write 148 #define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes 149 #define EPI_GPCFG_RD2CYC 0x00040000 // 2-Cycle Reads 150 #define EPI_GPCFG_MAXWAIT_M 0x0000FF00 // Maximum Wait 151 #define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size 152 #define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address 153 #define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide 154 #define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size 155 // cannot be used with 24-bit data 156 #define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size 157 // cannot be used with data sizes 158 // other than 8 159 #define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus 160 #define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7) 161 #define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15) 162 #define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23) 163 #define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31) 164 #define EPI_GPCFG_FRMCNT_S 22 165 #define EPI_GPCFG_MAXWAIT_S 8 166 167 //***************************************************************************** 168 // 169 // The following are defines for the bit fields in the EPI_O_SDRAMCFG register. 170 // 171 //***************************************************************************** 172 #define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range 173 #define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz 174 #define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz 175 #define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz 176 #define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter 177 #define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode 178 #define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM 179 #define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB) 180 #define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB) 181 #define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB) 182 #define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB) 183 #define EPI_SDRAMCFG_RFSH_S 16 184 185 //***************************************************************************** 186 // 187 // The following are defines for the bit fields in the EPI_O_HB8CFG register. 188 // 189 //***************************************************************************** 190 #define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable 191 #define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable 192 #define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity 193 #define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity 194 #define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait 195 #define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States 196 #define EPI_HB8CFG_WRWS_0 0x00000000 // No wait states 197 #define EPI_HB8CFG_WRWS_1 0x00000040 // 1 wait state 198 #define EPI_HB8CFG_WRWS_2 0x00000080 // 2 wait states 199 #define EPI_HB8CFG_WRWS_3 0x000000C0 // 3 wait states 200 #define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States 201 #define EPI_HB8CFG_RDWS_0 0x00000000 // No wait states 202 #define EPI_HB8CFG_RDWS_1 0x00000010 // 1 wait state 203 #define EPI_HB8CFG_RDWS_2 0x00000020 // 2 wait states 204 #define EPI_HB8CFG_RDWS_3 0x00000030 // 3 wait states 205 #define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode 206 #define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0] 207 #define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0] 208 #define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0] 209 #define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0] 210 #define EPI_HB8CFG_MAXWAIT_S 8 211 212 //***************************************************************************** 213 // 214 // The following are defines for the bit fields in the EPI_O_HB8CFG2 register. 215 // 216 //***************************************************************************** 217 #define EPI_HB8CFG2_WORD 0x80000000 // Word Access Mode 218 #define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate 219 #define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration 220 #define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration 221 #define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration 222 #define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration 223 #define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration 224 #define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity 225 #define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity 226 #define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States 227 #define EPI_HB8CFG2_WRWS_0 0x00000000 // No wait states 228 #define EPI_HB8CFG2_WRWS_1 0x00000040 // 1 wait state 229 #define EPI_HB8CFG2_WRWS_2 0x00000080 // 2 wait states 230 #define EPI_HB8CFG2_WRWS_3 0x000000C0 // 3 wait states 231 #define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States 232 #define EPI_HB8CFG2_RDWS_0 0x00000000 // No wait states 233 #define EPI_HB8CFG2_RDWS_1 0x00000010 // 1 wait state 234 #define EPI_HB8CFG2_RDWS_2 0x00000020 // 2 wait states 235 #define EPI_HB8CFG2_RDWS_3 0x00000030 // 3 wait states 236 237 //***************************************************************************** 238 // 239 // The following are defines for the bit fields in the EPI_O_HB16CFG2 register. 240 // 241 //***************************************************************************** 242 #define EPI_HB16CFG2_WORD 0x80000000 // Word Access Mode 243 #define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate 244 #define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration 245 #define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration 246 #define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration 247 #define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration 248 #define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration 249 #define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity 250 #define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity 251 #define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States 252 #define EPI_HB16CFG2_WRWS_0 0x00000000 // No wait states 253 #define EPI_HB16CFG2_WRWS_1 0x00000040 // 1 wait state 254 #define EPI_HB16CFG2_WRWS_2 0x00000080 // 2 wait states 255 #define EPI_HB16CFG2_WRWS_3 0x000000C0 // 3 wait states 256 #define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States 257 #define EPI_HB16CFG2_RDWS_0 0x00000000 // No wait states 258 #define EPI_HB16CFG2_RDWS_1 0x00000010 // 1 wait state 259 #define EPI_HB16CFG2_RDWS_2 0x00000020 // 2 wait states 260 #define EPI_HB16CFG2_RDWS_3 0x00000030 // 3 wait states 261 262 //***************************************************************************** 263 // 264 // The following are defines for the bit fields in the EPI_O_GPCFG2 register. 265 // 266 //***************************************************************************** 267 #define EPI_GPCFG2_WORD 0x80000000 // Word Access Mode 268 269 //***************************************************************************** 270 // 271 // The following are defines for the bit fields in the EPI_O_ADDRMAP register. 272 // 273 //***************************************************************************** 274 #define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size 275 #define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range: 276 // 0x00 to 0xFF 277 #define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range: 278 // 0x0000 to 0xFFFF 279 #define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range: 280 // 0x00.0000 to 0xFF.FFFF 281 #define EPI_ADDRMAP_EPSZ_512MB 0x000000C0 // 512 MB; lower address range: 282 // 0x000.0000 to 0x1FFF.FFFF 283 #define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address 284 #define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped 285 #define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000 286 #define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000 287 #define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size 288 #define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range: 289 // 0x00 to 0xFF 290 #define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range: 291 // 0x0000 to 0xFFFF 292 #define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range: 293 // 0x00.0000 to 0xFF.FFFF 294 #define EPI_ADDRMAP_ERSZ_512MB 0x0000000C // 512 MB; lower address range: 295 // 0x000.0000 to 0x1FFF.FFFF 296 #define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address 297 #define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped 298 #define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000 299 #define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000 300 301 //***************************************************************************** 302 // 303 // The following are defines for the bit fields in the EPI_O_RSIZE0 register. 304 // 305 //***************************************************************************** 306 #define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size 307 #define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits) 308 #define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits) 309 #define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits) 310 311 //***************************************************************************** 312 // 313 // The following are defines for the bit fields in the EPI_O_RADDR0 register. 314 // 315 //***************************************************************************** 316 #define EPI_RADDR0_ADDR_M 0x1FFFFFFF // Current Address 317 #define EPI_RADDR0_ADDR_S 0 318 319 //***************************************************************************** 320 // 321 // The following are defines for the bit fields in the EPI_O_RPSTD0 register. 322 // 323 //***************************************************************************** 324 #define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count 325 #define EPI_RPSTD0_POSTCNT_S 0 326 327 //***************************************************************************** 328 // 329 // The following are defines for the bit fields in the EPI_O_RSIZE1 register. 330 // 331 //***************************************************************************** 332 #define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size 333 #define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits) 334 #define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits) 335 #define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits) 336 337 //***************************************************************************** 338 // 339 // The following are defines for the bit fields in the EPI_O_RADDR1 register. 340 // 341 //***************************************************************************** 342 #define EPI_RADDR1_ADDR_M 0x1FFFFFFF // Current Address 343 #define EPI_RADDR1_ADDR_S 0 344 345 //***************************************************************************** 346 // 347 // The following are defines for the bit fields in the EPI_O_RPSTD1 register. 348 // 349 //***************************************************************************** 350 #define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count 351 #define EPI_RPSTD1_POSTCNT_S 0 352 353 //***************************************************************************** 354 // 355 // The following are defines for the bit fields in the EPI_O_STAT register. 356 // 357 //***************************************************************************** 358 #define EPI_STAT_CELOW 0x00000200 // Clock Enable Low 359 #define EPI_STAT_XFFULL 0x00000100 // External FIFO Full 360 #define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty 361 #define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence 362 #define EPI_STAT_WBUSY 0x00000020 // Write Busy 363 #define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy 364 #define EPI_STAT_ACTIVE 0x00000001 // Register Active 365 366 //***************************************************************************** 367 // 368 // The following are defines for the bit fields in the EPI_O_RFIFOCNT register. 369 // 370 //***************************************************************************** 371 #define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count 372 #define EPI_RFIFOCNT_COUNT_S 0 373 374 //***************************************************************************** 375 // 376 // The following are defines for the bit fields in the EPI_O_READFIFO0 377 // register. 378 // 379 //***************************************************************************** 380 #define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data 381 #define EPI_READFIFO0_DATA_S 0 382 383 //***************************************************************************** 384 // 385 // The following are defines for the bit fields in the EPI_O_READFIFO register. 386 // 387 //***************************************************************************** 388 #define EPI_READFIFO_DATA_M 0xFFFFFFFF // Reads Data 389 #define EPI_READFIFO_DATA_S 0 390 391 //***************************************************************************** 392 // 393 // The following are defines for the bit fields in the EPI_O_READFIFO1 394 // register. 395 // 396 //***************************************************************************** 397 #define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data 398 #define EPI_READFIFO1_DATA_S 0 399 400 //***************************************************************************** 401 // 402 // The following are defines for the bit fields in the EPI_O_READFIFO2 403 // register. 404 // 405 //***************************************************************************** 406 #define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data 407 #define EPI_READFIFO2_DATA_S 0 408 409 //***************************************************************************** 410 // 411 // The following are defines for the bit fields in the EPI_O_READFIFO3 412 // register. 413 // 414 //***************************************************************************** 415 #define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data 416 #define EPI_READFIFO3_DATA_S 0 417 418 //***************************************************************************** 419 // 420 // The following are defines for the bit fields in the EPI_O_READFIFO4 421 // register. 422 // 423 //***************************************************************************** 424 #define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data 425 #define EPI_READFIFO4_DATA_S 0 426 427 //***************************************************************************** 428 // 429 // The following are defines for the bit fields in the EPI_O_READFIFO5 430 // register. 431 // 432 //***************************************************************************** 433 #define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data 434 #define EPI_READFIFO5_DATA_S 0 435 436 //***************************************************************************** 437 // 438 // The following are defines for the bit fields in the EPI_O_READFIFO6 439 // register. 440 // 441 //***************************************************************************** 442 #define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data 443 #define EPI_READFIFO6_DATA_S 0 444 445 //***************************************************************************** 446 // 447 // The following are defines for the bit fields in the EPI_O_READFIFO7 448 // register. 449 // 450 //***************************************************************************** 451 #define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data 452 #define EPI_READFIFO7_DATA_S 0 453 454 //***************************************************************************** 455 // 456 // The following are defines for the bit fields in the EPI_O_FIFOLVL register. 457 // 458 //***************************************************************************** 459 #define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error 460 #define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error 461 #define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO 462 #define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Trigger when there are any 463 // spaces available in the WFIFO 464 #define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are up to 3 465 // spaces available in the WFIFO 466 #define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are up to 2 467 // spaces available in the WFIFO 468 #define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space 469 // available in the WFIFO 470 #define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO 471 #define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty 472 #define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more 473 // entries in the NBRFIFO 474 #define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more 475 // entries in the NBRFIFO 476 #define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more 477 // entries in the NBRFIFO 478 #define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more 479 // entries in the NBRFIFO 480 #define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more 481 // entries in the NBRFIFO 482 #define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries 483 // in the NBRFIFO 484 485 //***************************************************************************** 486 // 487 // The following are defines for the bit fields in the EPI_O_WFIFOCNT register. 488 // 489 //***************************************************************************** 490 #define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions 491 #define EPI_WFIFOCNT_WTAV_S 0 492 493 //***************************************************************************** 494 // 495 // The following are defines for the bit fields in the EPI_O_IM register. 496 // 497 //***************************************************************************** 498 #define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask 499 #define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask 500 #define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask 501 502 //***************************************************************************** 503 // 504 // The following are defines for the bit fields in the EPI_O_RIS register. 505 // 506 //***************************************************************************** 507 #define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status 508 #define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status 509 #define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status 510 511 //***************************************************************************** 512 // 513 // The following are defines for the bit fields in the EPI_O_MIS register. 514 // 515 //***************************************************************************** 516 #define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status 517 #define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status 518 #define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status 519 520 //***************************************************************************** 521 // 522 // The following are defines for the bit fields in the EPI_O_EISC register. 523 // 524 //***************************************************************************** 525 #define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error 526 #define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error 527 #define EPI_EISC_TOUT 0x00000001 // Timeout Error 528 529 //***************************************************************************** 530 // 531 // The following definitions are deprecated. 532 // 533 //***************************************************************************** 534 #ifndef DEPRECATED 535 536 //***************************************************************************** 537 // 538 // The following are deprecated defines for the bit fields in the EPI_O_BAUD 539 // register. 540 // 541 //***************************************************************************** 542 #define EPI_BAUD_COUNT_M 0x0000FFFF // Baud Rate Counter 543 #define EPI_BAUD_COUNT_S 0 544 545 #endif 546 547 #endif // __HW_EPI_H__ 548