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Searched refs:LPC_SYSCTL (Results 1 – 7 of 7) sorted by relevance

/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/inc/
A Dclock_15xx.h197 LPC_SYSCTL->USBCLKDIV = div; in Chip_Clock_SetUSBClockSource()
428 LPC_SYSCTL->SYSAHBCLKDIV = div; in Chip_Clock_SetSysClockDiv()
502 LPC_SYSCTL->SYSTICKCLKDIV = div; in Chip_Clock_SetSysTickClockDiv()
511 return LPC_SYSCTL->SYSTICKCLKDIV; in Chip_Clock_GetSysTickClockDiv()
528 LPC_SYSCTL->IOCONCLKDIV = div; in Chip_Clock_SetIOCONFiltClockDiv()
537 return LPC_SYSCTL->IOCONCLKDIV; in Chip_Clock_GetIOCONFiltClockDiv()
548 LPC_SYSCTL->ADCASYNCCLKDIV = div; in Chip_Clock_SetADCASYNCClockDiv()
557 return LPC_SYSCTL->ADCASYNCCLKDIV; in Chip_Clock_GetADCASYNCClockDiv()
601 return LPC_SYSCTL->UARTCLKDIV; in Chip_Clock_GetUARTFRGDivider()
612 LPC_SYSCTL->RTCOSCCTRL = 1; in Chip_Clock_EnableRTCOsc()
[all …]
A Dsysctl_15xx.h208 return LPC_SYSCTL->SYSRSTSTAT; in Chip_SYSCTL_GetSystemRSTStatus()
218 LPC_SYSCTL->SYSRSTSTAT = reset; in Chip_SYSCTL_ClearSystemRSTStatus()
228 return LPC_SYSCTL->PIOPORCAP[index]; in Chip_SYSCTL_GetPORPIOStatus()
271 LPC_SYSCTL->BODCTRL |= (1 << 4); in Chip_SYSCTL_EnableBODReset()
280 LPC_SYSCTL->BODCTRL &= ~(1 << 4); in Chip_SYSCTL_DisableBODReset()
290 LPC_SYSCTL->SYSTCKCAL = sysCalVal; in Chip_SYSCTL_SetSYSTCKCAL()
308 LPC_SYSCTL->NMISRC = intsrc; in Chip_SYSCTL_SetNMISource()
337 LPC_SYSCTL->FREQMECTRL = 0; in Chip_SYSCTL_StartFreqMeas()
537 return LPC_SYSCTL->PDWAKECFG; in Chip_SYSCTL_GetWakeup()
589 return LPC_SYSCTL->PDRUNCFG; in Chip_SYSCTL_GetPowerStates()
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A Dchip.h93 #define LPC_SYSCTL ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE) macro
/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/src/
A Dclock_15xx.c85 return Chip_Clock_GetPLLFreq(LPC_SYSCTL->SYSPLLCTRL, in Chip_Clock_GetSystemPLLOutClockRate()
98 return Chip_Clock_GetPLLFreq(LPC_SYSCTL->USBPLLCTRL, in Chip_Clock_GetUSBPLLOutClockRate()
263 LPC_SYSCTL->CLKOUTSEL[1] = srcClk - 4; in Chip_Clock_SetCLKOUTSource()
267 LPC_SYSCTL->CLKOUTSEL[0] = srcClk; in Chip_Clock_SetCLKOUTSource()
268 LPC_SYSCTL->CLKOUTSEL[1] = 0; in Chip_Clock_SetCLKOUTSource()
271 LPC_SYSCTL->CLKOUTDIV = div; in Chip_Clock_SetCLKOUTSource()
283 LPC_SYSCTL->SYSAHBCLKCTRL[0] |= (1 << clkEnab); in Chip_Clock_EnablePeriphClock()
296 LPC_SYSCTL->SYSAHBCLKCTRL[0] &= ~(1 << clkEnab); in Chip_Clock_DisablePeriphClock()
335 divmult = LPC_SYSCTL->FRGCTRL & 0xFFFF; in Chip_Clock_GetUARTBaseClockRate()
377 LPC_SYSCTL->FRGCTRL = 0; in Chip_Clock_SetUARTBaseClockRate()
[all …]
A Dsysctl_15xx.c75 LPC_SYSCTL->PRESETCTRL[1] |= (1 << ((uint32_t) periph - 32)); in Chip_SYSCTL_AssertPeriphReset()
78 LPC_SYSCTL->PRESETCTRL[0] |= (1 << (uint32_t) periph); in Chip_SYSCTL_AssertPeriphReset()
86 LPC_SYSCTL->PRESETCTRL[1] &= ~(1 << ((uint32_t) periph - 32)); in Chip_SYSCTL_DeassertPeriphReset()
89 LPC_SYSCTL->PRESETCTRL[0] &= ~(1 << (uint32_t) periph); in Chip_SYSCTL_DeassertPeriphReset()
97 LPC_SYSCTL->PDWAKECFG = PDWAKEUPUSEMASK | (wakeupmask & PDWAKEUPMASKTMP); in Chip_SYSCTL_SetWakeup()
105 pdrun = LPC_SYSCTL->PDRUNCFG & PDRUNCFGMASKTMP; in Chip_SYSCTL_PowerDown()
108 LPC_SYSCTL->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK); in Chip_SYSCTL_PowerDown()
116 pdrun = LPC_SYSCTL->PDRUNCFG & PDRUNCFGMASKTMP; in Chip_SYSCTL_PowerUp()
119 LPC_SYSCTL->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK); in Chip_SYSCTL_PowerUp()
/external/platform/lpc15xx/lpcopen/lpc_board_nxp_lpcxpresso_1549/src/
A Dboard_sysinit.c182 LPC_SYSCTL->SYSTICKCLKDIV = 1; in Board_SystemInit()
/external/platform/lpc15xx/lpcopen/periph_uart_rom_int/example/src/
A Duart_rom_int.c123 LPC_SYSCTL->FRGCTRL = ret_value; in setupUART()

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