Searched refs:MPU (Results 1 – 22 of 22) sorted by relevance
| /external/platform/pico/rp2_common/cmsis/stub/CMSIS/Core/Include/ |
| A D | mpu_armv7.h | 194 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; in ARM_MPU_Enable()
210 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in ARM_MPU_Disable()
220 MPU->RNR = rnr; in ARM_MPU_ClrRegion()
221 MPU->RASR = 0U; in ARM_MPU_ClrRegion()
230 MPU->RBAR = rbar; in ARM_MPU_SetRegion()
231 MPU->RASR = rasr; in ARM_MPU_SetRegion()
241 MPU->RNR = rnr; in ARM_MPU_SetRegionEx()
242 MPU->RBAR = rbar; in ARM_MPU_SetRegionEx()
243 MPU->RASR = rasr; in ARM_MPU_SetRegionEx()
268 ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); in ARM_MPU_Load()
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| A D | core_cm0plus.h | 659 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| /external/arch/arm/arm-m/CMSIS/Include/ |
| A D | mpu_armv7.h | 194 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; in ARM_MPU_Enable()
210 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in ARM_MPU_Disable()
220 MPU->RNR = rnr; in ARM_MPU_ClrRegion()
221 MPU->RASR = 0U; in ARM_MPU_ClrRegion()
230 MPU->RBAR = rbar; in ARM_MPU_SetRegion()
231 MPU->RASR = rasr; in ARM_MPU_SetRegion()
241 MPU->RNR = rnr; in ARM_MPU_SetRegionEx()
242 MPU->RBAR = rbar; in ARM_MPU_SetRegionEx()
243 MPU->RASR = rasr; in ARM_MPU_SetRegionEx()
268 ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); in ARM_MPU_Load()
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| A D | mpu_armv8.h | 133 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; in ARM_MPU_Enable()
149 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in ARM_MPU_Disable()
207 ARM_MPU_SetMemAttrEx(MPU, idx, attr); in ARM_MPU_SetMemAttr()
236 ARM_MPU_ClrRegionEx(MPU, rnr); in ARM_MPU_ClrRegion()
269 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); in ARM_MPU_SetRegion()
336 ARM_MPU_LoadEx(MPU, rnr, table, cnt); in ARM_MPU_Load()
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| A D | core_sc000.h | 674 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| A D | core_cm0plus.h | 659 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| A D | core_cm3.h | 1400 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| A D | core_sc300.h | 1383 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| A D | core_cm4.h | 1570 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| A D | core_armv8mbl.h | 1323 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| A D | core_cm23.h | 1398 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| A D | core_cm7.h | 1797 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| A D | core_cm33.h | 2220 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| A D | core_cm35p.h | 2220 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| A D | core_armv8mml.h | 2145 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| A D | core_armv81mml.h | 3115 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| A D | core_cm55.h | 3152 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
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| /external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Src/ |
| A D | stm32f7xx_hal_cortex.c | 285 MPU->RNR = MPU_Init->Number; in HAL_MPU_ConfigRegion()
298 MPU->RBAR = MPU_Init->BaseAddress; in HAL_MPU_ConfigRegion()
299 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | in HAL_MPU_ConfigRegion()
309 MPU->RBAR = 0x00; in HAL_MPU_ConfigRegion()
310 MPU->RASR = 0x00; in HAL_MPU_ConfigRegion()
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| /external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Inc/ |
| A D | stm32f7xx_hal_cortex.h | 446 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in HAL_MPU_Disable()
463 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; in HAL_MPU_Enable()
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| /external/platform/nrfx/doc/ |
| A D | nrfx_api.dox | 48 @defgroup nrf_mpu MPU
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| /external/platform/cc13xx/cc13xxware/startup_files/ |
| A D | startup_keil.s | 79 DCD MPUFaultIntHandler ; The MPU fault handler
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| /external/platform/nrfx/ |
| A D | CHANGELOG.md | 204 - Added HALs: BPROT, MPU, MWU.
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