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Searched refs:MPU_RASR_C_Pos (Results 1 – 10 of 10) sorted by relevance

/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Src/
A Dstm32f7xx_hal_cortex.c303 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | in HAL_MPU_ConfigRegion()
/external/arch/arm/arm-m/CMSIS/Include/
A Dcore_sc000.h599 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
600 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
A Dmpu_armv7.h91 (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
A Dcore_cm0plus.h585 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
586 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
A Dcore_cm3.h1222 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
1223 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
A Dcore_sc300.h1205 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
1206 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
A Dcore_cm4.h1280 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
1281 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
A Dcore_cm7.h1507 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
1508 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …
/external/platform/pico/rp2_common/cmsis/stub/CMSIS/Core/Include/
A Dmpu_armv7.h91 (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
A Dcore_cm0plus.h585 #define MPU_RASR_C_Pos 17U /*!< MPU … macro
586 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU …

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