1 //***************************************************************************** 2 // 3 // hw_nvic.h - Macros used when accessing the NVIC hardware. 4 // 5 // Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_NVIC_H__ 41 #define __HW_NVIC_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the NVIC register addresses. 46 // 47 //***************************************************************************** 48 #define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg 49 #define NVIC_ACTLR 0xE000E008 // Auxiliary Control 50 #define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status 51 // Register 52 #define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register 53 #define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register 54 #define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg 55 #define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable 56 #define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable 57 #define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable 58 #define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable 59 #define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable 60 #define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable 61 #define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable 62 #define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable 63 #define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable 64 #define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable 65 #define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending 66 #define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending 67 #define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending 68 #define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending 69 #define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending 70 #define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending 71 #define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending 72 #define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending 73 #define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending 74 #define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending 75 #define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit 76 #define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit 77 #define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit 78 #define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit 79 #define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit 80 #define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority 81 #define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority 82 #define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority 83 #define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority 84 #define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority 85 #define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority 86 #define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority 87 #define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority 88 #define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority 89 #define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority 90 #define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority 91 #define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority 92 #define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority 93 #define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority 94 #define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority 95 #define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority 96 #define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority 97 #define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority 98 #define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority 99 #define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority 100 #define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority 101 #define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority 102 #define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority 103 #define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority 104 #define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority 105 #define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority 106 #define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority 107 #define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority 108 #define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority 109 #define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority 110 #define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority 111 #define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority 112 #define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority 113 #define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority 114 #define NVIC_PRI34 0xE000E488 // Interrupt 136-138 Priority 115 #define NVIC_CPUID 0xE000ED00 // CPU ID Base 116 #define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State 117 #define NVIC_VTABLE 0xE000ED08 // Vector Table Offset 118 #define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset 119 // Control 120 #define NVIC_SYS_CTRL 0xE000ED10 // System Control 121 #define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control 122 #define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 123 #define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 124 #define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 125 #define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State 126 #define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status 127 #define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status 128 #define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register 129 #define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address 130 #define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address 131 #define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control 132 #define NVIC_MPU_TYPE 0xE000ED90 // MPU Type 133 #define NVIC_MPU_CTRL 0xE000ED94 // MPU Control 134 #define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number 135 #define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address 136 #define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size 137 #define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 138 #define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size 139 // Alias 1 140 #define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 141 #define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size 142 // Alias 2 143 #define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 144 #define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size 145 // Alias 3 146 #define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg 147 #define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select 148 #define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data 149 #define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control 150 #define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt 151 #define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control 152 #define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address 153 #define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status 154 // Control 155 156 //***************************************************************************** 157 // 158 // The following are defines for the bit fields in the NVIC_INT_TYPE register. 159 // 160 //***************************************************************************** 161 #define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) 162 #define NVIC_INT_TYPE_LINES_S 0 163 164 //***************************************************************************** 165 // 166 // The following are defines for the bit fields in the NVIC_ACTLR register. 167 // 168 //***************************************************************************** 169 #define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating 170 // Point 171 #define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL 172 #define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding 173 #define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer 174 #define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple 175 // Cycle Instructions 176 177 //***************************************************************************** 178 // 179 // The following are defines for the bit fields in the NVIC_ST_CTRL register. 180 // 181 //***************************************************************************** 182 #define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag 183 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source 184 #define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable 185 #define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable 186 187 //***************************************************************************** 188 // 189 // The following are defines for the bit fields in the NVIC_ST_RELOAD register. 190 // 191 //***************************************************************************** 192 #define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value 193 #define NVIC_ST_RELOAD_S 0 194 195 //***************************************************************************** 196 // 197 // The following are defines for the bit fields in the NVIC_ST_CURRENT 198 // register. 199 // 200 //***************************************************************************** 201 #define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value 202 #define NVIC_ST_CURRENT_S 0 203 204 //***************************************************************************** 205 // 206 // The following are defines for the bit fields in the NVIC_ST_CAL register. 207 // 208 //***************************************************************************** 209 #define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock 210 #define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew 211 #define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value 212 #define NVIC_ST_CAL_ONEMS_S 0 213 214 //***************************************************************************** 215 // 216 // The following are defines for the bit fields in the NVIC_EN0 register. 217 // 218 //***************************************************************************** 219 #define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable 220 #define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable 221 #define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable 222 #define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable 223 #define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable 224 #define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable 225 #define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable 226 #define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable 227 #define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable 228 #define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable 229 #define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable 230 #define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable 231 #define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable 232 #define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable 233 #define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable 234 #define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable 235 #define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable 236 #define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable 237 #define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable 238 #define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable 239 #define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable 240 #define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable 241 #define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable 242 #define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable 243 #define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable 244 #define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable 245 #define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable 246 #define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable 247 #define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable 248 #define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable 249 #define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable 250 #define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable 251 #define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable 252 253 //***************************************************************************** 254 // 255 // The following are defines for the bit fields in the NVIC_EN1 register. 256 // 257 //***************************************************************************** 258 #define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable 259 #define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable 260 #define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable 261 #define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable 262 #define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable 263 #define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable 264 #define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable 265 #define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable 266 #define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable 267 #define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable 268 #define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable 269 #define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable 270 #define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable 271 #define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable 272 #define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable 273 #define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable 274 #define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable 275 #define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable 276 #define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable 277 #define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable 278 #define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable 279 #define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable 280 #define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable 281 #define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable 282 283 //***************************************************************************** 284 // 285 // The following are defines for the bit fields in the NVIC_EN2 register. 286 // 287 //***************************************************************************** 288 #define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable 289 290 //***************************************************************************** 291 // 292 // The following are defines for the bit fields in the NVIC_EN3 register. 293 // 294 //***************************************************************************** 295 #define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable 296 297 //***************************************************************************** 298 // 299 // The following are defines for the bit fields in the NVIC_EN4 register. 300 // 301 //***************************************************************************** 302 #define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable 303 304 //***************************************************************************** 305 // 306 // The following are defines for the bit fields in the NVIC_DIS0 register. 307 // 308 //***************************************************************************** 309 #define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable 310 #define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable 311 #define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable 312 #define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable 313 #define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable 314 #define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable 315 #define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable 316 #define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable 317 #define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable 318 #define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable 319 #define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable 320 #define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable 321 #define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable 322 #define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable 323 #define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable 324 #define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable 325 #define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable 326 #define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable 327 #define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable 328 #define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable 329 #define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable 330 #define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable 331 #define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable 332 #define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable 333 #define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable 334 #define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable 335 #define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable 336 #define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable 337 #define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable 338 #define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable 339 #define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable 340 #define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable 341 #define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable 342 343 //***************************************************************************** 344 // 345 // The following are defines for the bit fields in the NVIC_DIS1 register. 346 // 347 //***************************************************************************** 348 #define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable 349 #define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable 350 #define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable 351 #define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable 352 #define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable 353 #define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable 354 #define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable 355 #define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable 356 #define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable 357 #define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable 358 #define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable 359 #define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable 360 #define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable 361 #define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable 362 #define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable 363 #define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable 364 #define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable 365 #define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable 366 #define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable 367 #define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable 368 #define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable 369 #define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable 370 #define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable 371 #define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable 372 #define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable 373 374 //***************************************************************************** 375 // 376 // The following are defines for the bit fields in the NVIC_DIS2 register. 377 // 378 //***************************************************************************** 379 #define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable 380 381 //***************************************************************************** 382 // 383 // The following are defines for the bit fields in the NVIC_DIS3 register. 384 // 385 //***************************************************************************** 386 #define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable 387 388 //***************************************************************************** 389 // 390 // The following are defines for the bit fields in the NVIC_DIS4 register. 391 // 392 //***************************************************************************** 393 #define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable 394 395 //***************************************************************************** 396 // 397 // The following are defines for the bit fields in the NVIC_PEND0 register. 398 // 399 //***************************************************************************** 400 #define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending 401 #define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend 402 #define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend 403 #define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend 404 #define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend 405 #define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend 406 #define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend 407 #define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend 408 #define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend 409 #define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend 410 #define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend 411 #define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend 412 #define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend 413 #define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend 414 #define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend 415 #define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend 416 #define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend 417 #define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend 418 #define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend 419 #define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend 420 #define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend 421 #define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend 422 #define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend 423 #define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend 424 #define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend 425 #define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend 426 #define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend 427 #define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend 428 #define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend 429 #define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend 430 #define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend 431 #define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend 432 #define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend 433 434 //***************************************************************************** 435 // 436 // The following are defines for the bit fields in the NVIC_PEND1 register. 437 // 438 //***************************************************************************** 439 #define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending 440 #define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend 441 #define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend 442 #define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend 443 #define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend 444 #define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend 445 #define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend 446 #define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend 447 #define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend 448 #define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend 449 #define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend 450 #define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend 451 #define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend 452 #define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend 453 #define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend 454 #define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend 455 #define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend 456 #define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend 457 #define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend 458 #define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend 459 #define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend 460 #define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend 461 #define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend 462 #define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend 463 #define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend 464 465 //***************************************************************************** 466 // 467 // The following are defines for the bit fields in the NVIC_PEND2 register. 468 // 469 //***************************************************************************** 470 #define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending 471 472 //***************************************************************************** 473 // 474 // The following are defines for the bit fields in the NVIC_PEND3 register. 475 // 476 //***************************************************************************** 477 #define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending 478 479 //***************************************************************************** 480 // 481 // The following are defines for the bit fields in the NVIC_PEND4 register. 482 // 483 //***************************************************************************** 484 #define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending 485 486 //***************************************************************************** 487 // 488 // The following are defines for the bit fields in the NVIC_UNPEND0 register. 489 // 490 //***************************************************************************** 491 #define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending 492 #define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend 493 #define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend 494 #define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend 495 #define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend 496 #define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend 497 #define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend 498 #define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend 499 #define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend 500 #define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend 501 #define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend 502 #define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend 503 #define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend 504 #define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend 505 #define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend 506 #define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend 507 #define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend 508 #define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend 509 #define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend 510 #define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend 511 #define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend 512 #define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend 513 #define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend 514 #define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend 515 #define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend 516 #define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend 517 #define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend 518 #define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend 519 #define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend 520 #define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend 521 #define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend 522 #define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend 523 #define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend 524 525 //***************************************************************************** 526 // 527 // The following are defines for the bit fields in the NVIC_UNPEND1 register. 528 // 529 //***************************************************************************** 530 #define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending 531 #define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend 532 #define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend 533 #define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend 534 #define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend 535 #define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend 536 #define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend 537 #define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend 538 #define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend 539 #define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend 540 #define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend 541 #define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend 542 #define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend 543 #define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend 544 #define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend 545 #define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend 546 #define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend 547 #define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend 548 #define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend 549 #define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend 550 #define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend 551 #define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend 552 #define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend 553 #define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend 554 #define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend 555 556 //***************************************************************************** 557 // 558 // The following are defines for the bit fields in the NVIC_UNPEND2 register. 559 // 560 //***************************************************************************** 561 #define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending 562 563 //***************************************************************************** 564 // 565 // The following are defines for the bit fields in the NVIC_UNPEND3 register. 566 // 567 //***************************************************************************** 568 #define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending 569 570 //***************************************************************************** 571 // 572 // The following are defines for the bit fields in the NVIC_UNPEND4 register. 573 // 574 //***************************************************************************** 575 #define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending 576 577 //***************************************************************************** 578 // 579 // The following are defines for the bit fields in the NVIC_ACTIVE0 register. 580 // 581 //***************************************************************************** 582 #define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active 583 #define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active 584 #define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active 585 #define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active 586 #define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active 587 #define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active 588 #define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active 589 #define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active 590 #define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active 591 #define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active 592 #define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active 593 #define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active 594 #define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active 595 #define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active 596 #define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active 597 #define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active 598 #define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active 599 #define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active 600 #define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active 601 #define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active 602 #define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active 603 #define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active 604 #define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active 605 #define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active 606 #define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active 607 #define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active 608 #define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active 609 #define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active 610 #define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active 611 #define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active 612 #define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active 613 #define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active 614 #define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active 615 616 //***************************************************************************** 617 // 618 // The following are defines for the bit fields in the NVIC_ACTIVE1 register. 619 // 620 //***************************************************************************** 621 #define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active 622 #define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active 623 #define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active 624 #define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active 625 #define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active 626 #define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active 627 #define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active 628 #define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active 629 #define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active 630 #define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active 631 #define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active 632 #define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active 633 #define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active 634 #define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active 635 #define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active 636 #define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active 637 #define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active 638 #define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active 639 #define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active 640 #define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active 641 #define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active 642 #define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active 643 #define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active 644 #define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active 645 #define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active 646 647 //***************************************************************************** 648 // 649 // The following are defines for the bit fields in the NVIC_ACTIVE2 register. 650 // 651 //***************************************************************************** 652 #define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active 653 654 //***************************************************************************** 655 // 656 // The following are defines for the bit fields in the NVIC_ACTIVE3 register. 657 // 658 //***************************************************************************** 659 #define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active 660 661 //***************************************************************************** 662 // 663 // The following are defines for the bit fields in the NVIC_ACTIVE4 register. 664 // 665 //***************************************************************************** 666 #define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active 667 668 //***************************************************************************** 669 // 670 // The following are defines for the bit fields in the NVIC_PRI0 register. 671 // 672 //***************************************************************************** 673 #define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask 674 #define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask 675 #define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask 676 #define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask 677 #define NVIC_PRI0_INT3_S 29 678 #define NVIC_PRI0_INT2_S 21 679 #define NVIC_PRI0_INT1_S 13 680 #define NVIC_PRI0_INT0_S 5 681 682 //***************************************************************************** 683 // 684 // The following are defines for the bit fields in the NVIC_PRI1 register. 685 // 686 //***************************************************************************** 687 #define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask 688 #define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask 689 #define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask 690 #define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask 691 #define NVIC_PRI1_INT7_S 29 692 #define NVIC_PRI1_INT6_S 21 693 #define NVIC_PRI1_INT5_S 13 694 #define NVIC_PRI1_INT4_S 5 695 696 //***************************************************************************** 697 // 698 // The following are defines for the bit fields in the NVIC_PRI2 register. 699 // 700 //***************************************************************************** 701 #define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask 702 #define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask 703 #define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask 704 #define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask 705 #define NVIC_PRI2_INT11_S 29 706 #define NVIC_PRI2_INT10_S 21 707 #define NVIC_PRI2_INT9_S 13 708 #define NVIC_PRI2_INT8_S 5 709 710 //***************************************************************************** 711 // 712 // The following are defines for the bit fields in the NVIC_PRI3 register. 713 // 714 //***************************************************************************** 715 #define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask 716 #define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask 717 #define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask 718 #define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask 719 #define NVIC_PRI3_INT15_S 29 720 #define NVIC_PRI3_INT14_S 21 721 #define NVIC_PRI3_INT13_S 13 722 #define NVIC_PRI3_INT12_S 5 723 724 //***************************************************************************** 725 // 726 // The following are defines for the bit fields in the NVIC_PRI4 register. 727 // 728 //***************************************************************************** 729 #define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask 730 #define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask 731 #define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask 732 #define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask 733 #define NVIC_PRI4_INT19_S 29 734 #define NVIC_PRI4_INT18_S 21 735 #define NVIC_PRI4_INT17_S 13 736 #define NVIC_PRI4_INT16_S 5 737 738 //***************************************************************************** 739 // 740 // The following are defines for the bit fields in the NVIC_PRI5 register. 741 // 742 //***************************************************************************** 743 #define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask 744 #define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask 745 #define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask 746 #define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask 747 #define NVIC_PRI5_INT23_S 29 748 #define NVIC_PRI5_INT22_S 21 749 #define NVIC_PRI5_INT21_S 13 750 #define NVIC_PRI5_INT20_S 5 751 752 //***************************************************************************** 753 // 754 // The following are defines for the bit fields in the NVIC_PRI6 register. 755 // 756 //***************************************************************************** 757 #define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask 758 #define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask 759 #define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask 760 #define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask 761 #define NVIC_PRI6_INT27_S 29 762 #define NVIC_PRI6_INT26_S 21 763 #define NVIC_PRI6_INT25_S 13 764 #define NVIC_PRI6_INT24_S 5 765 766 //***************************************************************************** 767 // 768 // The following are defines for the bit fields in the NVIC_PRI7 register. 769 // 770 //***************************************************************************** 771 #define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask 772 #define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask 773 #define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask 774 #define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask 775 #define NVIC_PRI7_INT31_S 29 776 #define NVIC_PRI7_INT30_S 21 777 #define NVIC_PRI7_INT29_S 13 778 #define NVIC_PRI7_INT28_S 5 779 780 //***************************************************************************** 781 // 782 // The following are defines for the bit fields in the NVIC_PRI8 register. 783 // 784 //***************************************************************************** 785 #define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask 786 #define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask 787 #define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask 788 #define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask 789 #define NVIC_PRI8_INT35_S 29 790 #define NVIC_PRI8_INT34_S 21 791 #define NVIC_PRI8_INT33_S 13 792 #define NVIC_PRI8_INT32_S 5 793 794 //***************************************************************************** 795 // 796 // The following are defines for the bit fields in the NVIC_PRI9 register. 797 // 798 //***************************************************************************** 799 #define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask 800 #define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask 801 #define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask 802 #define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask 803 #define NVIC_PRI9_INT39_S 29 804 #define NVIC_PRI9_INT38_S 21 805 #define NVIC_PRI9_INT37_S 13 806 #define NVIC_PRI9_INT36_S 5 807 808 //***************************************************************************** 809 // 810 // The following are defines for the bit fields in the NVIC_PRI10 register. 811 // 812 //***************************************************************************** 813 #define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask 814 #define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask 815 #define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask 816 #define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask 817 #define NVIC_PRI10_INT43_S 29 818 #define NVIC_PRI10_INT42_S 21 819 #define NVIC_PRI10_INT41_S 13 820 #define NVIC_PRI10_INT40_S 5 821 822 //***************************************************************************** 823 // 824 // The following are defines for the bit fields in the NVIC_PRI11 register. 825 // 826 //***************************************************************************** 827 #define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask 828 #define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask 829 #define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask 830 #define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask 831 #define NVIC_PRI11_INT47_S 29 832 #define NVIC_PRI11_INT46_S 21 833 #define NVIC_PRI11_INT45_S 13 834 #define NVIC_PRI11_INT44_S 5 835 836 //***************************************************************************** 837 // 838 // The following are defines for the bit fields in the NVIC_PRI12 register. 839 // 840 //***************************************************************************** 841 #define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask 842 #define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask 843 #define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask 844 #define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask 845 #define NVIC_PRI12_INT51_S 29 846 #define NVIC_PRI12_INT50_S 21 847 #define NVIC_PRI12_INT49_S 13 848 #define NVIC_PRI12_INT48_S 5 849 850 //***************************************************************************** 851 // 852 // The following are defines for the bit fields in the NVIC_PRI13 register. 853 // 854 //***************************************************************************** 855 #define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask 856 #define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask 857 #define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask 858 #define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask 859 #define NVIC_PRI13_INT55_S 29 860 #define NVIC_PRI13_INT54_S 21 861 #define NVIC_PRI13_INT53_S 13 862 #define NVIC_PRI13_INT52_S 5 863 864 //***************************************************************************** 865 // 866 // The following are defines for the bit fields in the NVIC_PRI14 register. 867 // 868 //***************************************************************************** 869 #define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask 870 #define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask 871 #define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask 872 #define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask 873 #define NVIC_PRI14_INTD_S 29 874 #define NVIC_PRI14_INTC_S 21 875 #define NVIC_PRI14_INTB_S 13 876 #define NVIC_PRI14_INTA_S 5 877 878 //***************************************************************************** 879 // 880 // The following are defines for the bit fields in the NVIC_PRI15 register. 881 // 882 //***************************************************************************** 883 #define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask 884 #define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask 885 #define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask 886 #define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask 887 #define NVIC_PRI15_INTD_S 29 888 #define NVIC_PRI15_INTC_S 21 889 #define NVIC_PRI15_INTB_S 13 890 #define NVIC_PRI15_INTA_S 5 891 892 //***************************************************************************** 893 // 894 // The following are defines for the bit fields in the NVIC_PRI16 register. 895 // 896 //***************************************************************************** 897 #define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask 898 #define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask 899 #define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask 900 #define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask 901 #define NVIC_PRI16_INTD_S 29 902 #define NVIC_PRI16_INTC_S 21 903 #define NVIC_PRI16_INTB_S 13 904 #define NVIC_PRI16_INTA_S 5 905 906 //***************************************************************************** 907 // 908 // The following are defines for the bit fields in the NVIC_PRI17 register. 909 // 910 //***************************************************************************** 911 #define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask 912 #define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask 913 #define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask 914 #define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask 915 #define NVIC_PRI17_INTD_S 29 916 #define NVIC_PRI17_INTC_S 21 917 #define NVIC_PRI17_INTB_S 13 918 #define NVIC_PRI17_INTA_S 5 919 920 //***************************************************************************** 921 // 922 // The following are defines for the bit fields in the NVIC_PRI18 register. 923 // 924 //***************************************************************************** 925 #define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask 926 #define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask 927 #define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask 928 #define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask 929 #define NVIC_PRI18_INTD_S 29 930 #define NVIC_PRI18_INTC_S 21 931 #define NVIC_PRI18_INTB_S 13 932 #define NVIC_PRI18_INTA_S 5 933 934 //***************************************************************************** 935 // 936 // The following are defines for the bit fields in the NVIC_PRI19 register. 937 // 938 //***************************************************************************** 939 #define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask 940 #define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask 941 #define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask 942 #define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask 943 #define NVIC_PRI19_INTD_S 29 944 #define NVIC_PRI19_INTC_S 21 945 #define NVIC_PRI19_INTB_S 13 946 #define NVIC_PRI19_INTA_S 5 947 948 //***************************************************************************** 949 // 950 // The following are defines for the bit fields in the NVIC_PRI20 register. 951 // 952 //***************************************************************************** 953 #define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask 954 #define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask 955 #define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask 956 #define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask 957 #define NVIC_PRI20_INTD_S 29 958 #define NVIC_PRI20_INTC_S 21 959 #define NVIC_PRI20_INTB_S 13 960 #define NVIC_PRI20_INTA_S 5 961 962 //***************************************************************************** 963 // 964 // The following are defines for the bit fields in the NVIC_PRI21 register. 965 // 966 //***************************************************************************** 967 #define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask 968 #define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask 969 #define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask 970 #define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask 971 #define NVIC_PRI21_INTD_S 29 972 #define NVIC_PRI21_INTC_S 21 973 #define NVIC_PRI21_INTB_S 13 974 #define NVIC_PRI21_INTA_S 5 975 976 //***************************************************************************** 977 // 978 // The following are defines for the bit fields in the NVIC_PRI22 register. 979 // 980 //***************************************************************************** 981 #define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask 982 #define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask 983 #define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask 984 #define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask 985 #define NVIC_PRI22_INTD_S 29 986 #define NVIC_PRI22_INTC_S 21 987 #define NVIC_PRI22_INTB_S 13 988 #define NVIC_PRI22_INTA_S 5 989 990 //***************************************************************************** 991 // 992 // The following are defines for the bit fields in the NVIC_PRI23 register. 993 // 994 //***************************************************************************** 995 #define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask 996 #define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask 997 #define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask 998 #define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask 999 #define NVIC_PRI23_INTD_S 29 1000 #define NVIC_PRI23_INTC_S 21 1001 #define NVIC_PRI23_INTB_S 13 1002 #define NVIC_PRI23_INTA_S 5 1003 1004 //***************************************************************************** 1005 // 1006 // The following are defines for the bit fields in the NVIC_PRI24 register. 1007 // 1008 //***************************************************************************** 1009 #define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask 1010 #define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask 1011 #define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask 1012 #define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask 1013 #define NVIC_PRI24_INTD_S 29 1014 #define NVIC_PRI24_INTC_S 21 1015 #define NVIC_PRI24_INTB_S 13 1016 #define NVIC_PRI24_INTA_S 5 1017 1018 //***************************************************************************** 1019 // 1020 // The following are defines for the bit fields in the NVIC_PRI25 register. 1021 // 1022 //***************************************************************************** 1023 #define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask 1024 #define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask 1025 #define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask 1026 #define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask 1027 #define NVIC_PRI25_INTD_S 29 1028 #define NVIC_PRI25_INTC_S 21 1029 #define NVIC_PRI25_INTB_S 13 1030 #define NVIC_PRI25_INTA_S 5 1031 1032 //***************************************************************************** 1033 // 1034 // The following are defines for the bit fields in the NVIC_PRI26 register. 1035 // 1036 //***************************************************************************** 1037 #define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask 1038 #define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask 1039 #define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask 1040 #define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask 1041 #define NVIC_PRI26_INTD_S 29 1042 #define NVIC_PRI26_INTC_S 21 1043 #define NVIC_PRI26_INTB_S 13 1044 #define NVIC_PRI26_INTA_S 5 1045 1046 //***************************************************************************** 1047 // 1048 // The following are defines for the bit fields in the NVIC_PRI27 register. 1049 // 1050 //***************************************************************************** 1051 #define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask 1052 #define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask 1053 #define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask 1054 #define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask 1055 #define NVIC_PRI27_INTD_S 29 1056 #define NVIC_PRI27_INTC_S 21 1057 #define NVIC_PRI27_INTB_S 13 1058 #define NVIC_PRI27_INTA_S 5 1059 1060 //***************************************************************************** 1061 // 1062 // The following are defines for the bit fields in the NVIC_PRI28 register. 1063 // 1064 //***************************************************************************** 1065 #define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask 1066 #define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask 1067 #define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask 1068 #define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask 1069 #define NVIC_PRI28_INTD_S 29 1070 #define NVIC_PRI28_INTC_S 21 1071 #define NVIC_PRI28_INTB_S 13 1072 #define NVIC_PRI28_INTA_S 5 1073 1074 //***************************************************************************** 1075 // 1076 // The following are defines for the bit fields in the NVIC_PRI29 register. 1077 // 1078 //***************************************************************************** 1079 #define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask 1080 #define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask 1081 #define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask 1082 #define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask 1083 #define NVIC_PRI29_INTD_S 29 1084 #define NVIC_PRI29_INTC_S 21 1085 #define NVIC_PRI29_INTB_S 13 1086 #define NVIC_PRI29_INTA_S 5 1087 1088 //***************************************************************************** 1089 // 1090 // The following are defines for the bit fields in the NVIC_PRI30 register. 1091 // 1092 //***************************************************************************** 1093 #define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask 1094 #define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask 1095 #define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask 1096 #define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask 1097 #define NVIC_PRI30_INTD_S 29 1098 #define NVIC_PRI30_INTC_S 21 1099 #define NVIC_PRI30_INTB_S 13 1100 #define NVIC_PRI30_INTA_S 5 1101 1102 //***************************************************************************** 1103 // 1104 // The following are defines for the bit fields in the NVIC_PRI31 register. 1105 // 1106 //***************************************************************************** 1107 #define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask 1108 #define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask 1109 #define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask 1110 #define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask 1111 #define NVIC_PRI31_INTD_S 29 1112 #define NVIC_PRI31_INTC_S 21 1113 #define NVIC_PRI31_INTB_S 13 1114 #define NVIC_PRI31_INTA_S 5 1115 1116 //***************************************************************************** 1117 // 1118 // The following are defines for the bit fields in the NVIC_PRI32 register. 1119 // 1120 //***************************************************************************** 1121 #define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask 1122 #define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask 1123 #define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask 1124 #define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask 1125 #define NVIC_PRI32_INTD_S 29 1126 #define NVIC_PRI32_INTC_S 21 1127 #define NVIC_PRI32_INTB_S 13 1128 #define NVIC_PRI32_INTA_S 5 1129 1130 //***************************************************************************** 1131 // 1132 // The following are defines for the bit fields in the NVIC_PRI33 register. 1133 // 1134 //***************************************************************************** 1135 #define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt 1136 // [4n+3] 1137 #define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt 1138 // [4n+2] 1139 #define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt 1140 // [4n+1] 1141 #define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt 1142 // [4n] 1143 #define NVIC_PRI33_INTD_S 29 1144 #define NVIC_PRI33_INTC_S 21 1145 #define NVIC_PRI33_INTB_S 13 1146 #define NVIC_PRI33_INTA_S 5 1147 1148 //***************************************************************************** 1149 // 1150 // The following are defines for the bit fields in the NVIC_PRI34 register. 1151 // 1152 //***************************************************************************** 1153 #define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt 1154 // [4n+3] 1155 #define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt 1156 // [4n+2] 1157 #define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt 1158 // [4n+1] 1159 #define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt 1160 // [4n] 1161 #define NVIC_PRI34_INTD_S 29 1162 #define NVIC_PRI34_INTC_S 21 1163 #define NVIC_PRI34_INTB_S 13 1164 #define NVIC_PRI34_INTA_S 5 1165 1166 //***************************************************************************** 1167 // 1168 // The following are defines for the bit fields in the NVIC_CPUID register. 1169 // 1170 //***************************************************************************** 1171 #define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code 1172 #define NVIC_CPUID_IMP_ARM 0x41000000 // ARM 1173 #define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number 1174 #define NVIC_CPUID_CON_M 0x000F0000 // Constant 1175 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number 1176 #define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor 1177 #define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor 1178 #define NVIC_CPUID_REV_M 0x0000000F // Revision Number 1179 1180 //***************************************************************************** 1181 // 1182 // The following are defines for the bit fields in the NVIC_INT_CTRL register. 1183 // 1184 //***************************************************************************** 1185 #define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending 1186 #define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending 1187 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending 1188 #define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending 1189 #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending 1190 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling 1191 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending 1192 #define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number 1193 #define NVIC_INT_CTRL_VEC_PEN_NMI \ 1194 0x00002000 // NMI 1195 #define NVIC_INT_CTRL_VEC_PEN_HARD \ 1196 0x00003000 // Hard fault 1197 #define NVIC_INT_CTRL_VEC_PEN_MEM \ 1198 0x00004000 // Memory management fault 1199 #define NVIC_INT_CTRL_VEC_PEN_BUS \ 1200 0x00005000 // Bus fault 1201 #define NVIC_INT_CTRL_VEC_PEN_USG \ 1202 0x00006000 // Usage fault 1203 #define NVIC_INT_CTRL_VEC_PEN_SVC \ 1204 0x0000B000 // SVCall 1205 #define NVIC_INT_CTRL_VEC_PEN_PNDSV \ 1206 0x0000E000 // PendSV 1207 #define NVIC_INT_CTRL_VEC_PEN_TICK \ 1208 0x0000F000 // SysTick 1209 #define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base 1210 #define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number 1211 #define NVIC_INT_CTRL_VEC_PEN_S 12 1212 #define NVIC_INT_CTRL_VEC_ACT_S 0 1213 1214 //***************************************************************************** 1215 // 1216 // The following are defines for the bit fields in the NVIC_VTABLE register. 1217 // 1218 //***************************************************************************** 1219 #define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base 1220 #define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset 1221 #define NVIC_VTABLE_OFFSET_S 10 1222 1223 //***************************************************************************** 1224 // 1225 // The following are defines for the bit fields in the NVIC_APINT register. 1226 // 1227 //***************************************************************************** 1228 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key 1229 #define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key 1230 #define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess 1231 #define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping 1232 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split 1233 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split 1234 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split 1235 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split 1236 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split 1237 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split 1238 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split 1239 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split 1240 #define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request 1241 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault 1242 #define NVIC_APINT_VECT_RESET 0x00000001 // System Reset 1243 1244 //***************************************************************************** 1245 // 1246 // The following are defines for the bit fields in the NVIC_SYS_CTRL register. 1247 // 1248 //***************************************************************************** 1249 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending 1250 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable 1251 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit 1252 1253 //***************************************************************************** 1254 // 1255 // The following are defines for the bit fields in the NVIC_CFG_CTRL register. 1256 // 1257 //***************************************************************************** 1258 #define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception 1259 // Entry 1260 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and 1261 // Fault 1262 #define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 1263 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access 1264 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger 1265 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control 1266 1267 //***************************************************************************** 1268 // 1269 // The following are defines for the bit fields in the NVIC_SYS_PRI1 register. 1270 // 1271 //***************************************************************************** 1272 #define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority 1273 #define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority 1274 #define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority 1275 #define NVIC_SYS_PRI1_USAGE_S 21 1276 #define NVIC_SYS_PRI1_BUS_S 13 1277 #define NVIC_SYS_PRI1_MEM_S 5 1278 1279 //***************************************************************************** 1280 // 1281 // The following are defines for the bit fields in the NVIC_SYS_PRI2 register. 1282 // 1283 //***************************************************************************** 1284 #define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority 1285 #define NVIC_SYS_PRI2_SVC_S 29 1286 1287 //***************************************************************************** 1288 // 1289 // The following are defines for the bit fields in the NVIC_SYS_PRI3 register. 1290 // 1291 //***************************************************************************** 1292 #define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority 1293 #define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority 1294 #define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority 1295 #define NVIC_SYS_PRI3_TICK_S 29 1296 #define NVIC_SYS_PRI3_PENDSV_S 21 1297 #define NVIC_SYS_PRI3_DEBUG_S 5 1298 1299 //***************************************************************************** 1300 // 1301 // The following are defines for the bit fields in the NVIC_SYS_HND_CTRL 1302 // register. 1303 // 1304 //***************************************************************************** 1305 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable 1306 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable 1307 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable 1308 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending 1309 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending 1310 #define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending 1311 #define NVIC_SYS_HND_CTRL_USAGEP \ 1312 0x00001000 // Usage Fault Pending 1313 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active 1314 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active 1315 #define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active 1316 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active 1317 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active 1318 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active 1319 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active 1320 1321 //***************************************************************************** 1322 // 1323 // The following are defines for the bit fields in the NVIC_FAULT_STAT 1324 // register. 1325 // 1326 //***************************************************************************** 1327 #define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault 1328 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault 1329 #define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault 1330 #define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault 1331 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault 1332 #define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage 1333 // Fault 1334 #define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid 1335 #define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy 1336 // State Preservation 1337 #define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault 1338 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault 1339 #define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error 1340 #define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error 1341 #define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error 1342 #define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address 1343 // Register Valid 1344 #define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on 1345 // Floating-Point Lazy State 1346 // Preservation 1347 #define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation 1348 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation 1349 #define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation 1350 #define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation 1351 1352 //***************************************************************************** 1353 // 1354 // The following are defines for the bit fields in the NVIC_HFAULT_STAT 1355 // register. 1356 // 1357 //***************************************************************************** 1358 #define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event 1359 #define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault 1360 #define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault 1361 1362 //***************************************************************************** 1363 // 1364 // The following are defines for the bit fields in the NVIC_DEBUG_STAT 1365 // register. 1366 // 1367 //***************************************************************************** 1368 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted 1369 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch 1370 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match 1371 #define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction 1372 #define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request 1373 1374 //***************************************************************************** 1375 // 1376 // The following are defines for the bit fields in the NVIC_MM_ADDR register. 1377 // 1378 //***************************************************************************** 1379 #define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address 1380 #define NVIC_MM_ADDR_S 0 1381 1382 //***************************************************************************** 1383 // 1384 // The following are defines for the bit fields in the NVIC_FAULT_ADDR 1385 // register. 1386 // 1387 //***************************************************************************** 1388 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address 1389 #define NVIC_FAULT_ADDR_S 0 1390 1391 //***************************************************************************** 1392 // 1393 // The following are defines for the bit fields in the NVIC_CPAC register. 1394 // 1395 //***************************************************************************** 1396 #define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access 1397 // Privilege 1398 #define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied 1399 #define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only 1400 #define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access 1401 #define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access 1402 // Privilege 1403 #define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied 1404 #define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only 1405 #define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access 1406 1407 //***************************************************************************** 1408 // 1409 // The following are defines for the bit fields in the NVIC_MPU_TYPE register. 1410 // 1411 //***************************************************************************** 1412 #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions 1413 #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions 1414 #define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU 1415 #define NVIC_MPU_TYPE_IREGION_S 16 1416 #define NVIC_MPU_TYPE_DREGION_S 8 1417 1418 //***************************************************************************** 1419 // 1420 // The following are defines for the bit fields in the NVIC_MPU_CTRL register. 1421 // 1422 //***************************************************************************** 1423 #define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region 1424 #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults 1425 #define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable 1426 1427 //***************************************************************************** 1428 // 1429 // The following are defines for the bit fields in the NVIC_MPU_NUMBER 1430 // register. 1431 // 1432 //***************************************************************************** 1433 #define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access 1434 #define NVIC_MPU_NUMBER_S 0 1435 1436 //***************************************************************************** 1437 // 1438 // The following are defines for the bit fields in the NVIC_MPU_BASE register. 1439 // 1440 //***************************************************************************** 1441 #define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask 1442 #define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid 1443 #define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number 1444 #define NVIC_MPU_BASE_ADDR_S 5 1445 #define NVIC_MPU_BASE_REGION_S 0 1446 1447 //***************************************************************************** 1448 // 1449 // The following are defines for the bit fields in the NVIC_MPU_ATTR register. 1450 // 1451 //***************************************************************************** 1452 #define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes 1453 #define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable 1454 #define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege 1455 #define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access 1456 #define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none 1457 #define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only 1458 #define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw 1459 #define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none 1460 #define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro 1461 #define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask 1462 #define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable 1463 #define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable 1464 #define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable 1465 #define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits 1466 #define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable 1467 #define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable 1468 #define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable 1469 #define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable 1470 #define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable 1471 #define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable 1472 #define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable 1473 #define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable 1474 #define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask 1475 #define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes 1476 #define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes 1477 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes 1478 #define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes 1479 #define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes 1480 #define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes 1481 #define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes 1482 #define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes 1483 #define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes 1484 #define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes 1485 #define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes 1486 #define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes 1487 #define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes 1488 #define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes 1489 #define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes 1490 #define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes 1491 #define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes 1492 #define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes 1493 #define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes 1494 #define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes 1495 #define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes 1496 #define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes 1497 #define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes 1498 #define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes 1499 #define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes 1500 #define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes 1501 #define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes 1502 #define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes 1503 #define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable 1504 1505 //***************************************************************************** 1506 // 1507 // The following are defines for the bit fields in the NVIC_MPU_BASE1 register. 1508 // 1509 //***************************************************************************** 1510 #define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask 1511 #define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid 1512 #define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number 1513 #define NVIC_MPU_BASE1_ADDR_S 5 1514 #define NVIC_MPU_BASE1_REGION_S 0 1515 1516 //***************************************************************************** 1517 // 1518 // The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. 1519 // 1520 //***************************************************************************** 1521 #define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable 1522 #define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege 1523 #define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask 1524 #define NVIC_MPU_ATTR1_SHAREABLE \ 1525 0x00040000 // Shareable 1526 #define NVIC_MPU_ATTR1_CACHEABLE \ 1527 0x00020000 // Cacheable 1528 #define NVIC_MPU_ATTR1_BUFFRABLE \ 1529 0x00010000 // Bufferable 1530 #define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits 1531 #define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask 1532 #define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable 1533 1534 //***************************************************************************** 1535 // 1536 // The following are defines for the bit fields in the NVIC_MPU_BASE2 register. 1537 // 1538 //***************************************************************************** 1539 #define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask 1540 #define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid 1541 #define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number 1542 #define NVIC_MPU_BASE2_ADDR_S 5 1543 #define NVIC_MPU_BASE2_REGION_S 0 1544 1545 //***************************************************************************** 1546 // 1547 // The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. 1548 // 1549 //***************************************************************************** 1550 #define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable 1551 #define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege 1552 #define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask 1553 #define NVIC_MPU_ATTR2_SHAREABLE \ 1554 0x00040000 // Shareable 1555 #define NVIC_MPU_ATTR2_CACHEABLE \ 1556 0x00020000 // Cacheable 1557 #define NVIC_MPU_ATTR2_BUFFRABLE \ 1558 0x00010000 // Bufferable 1559 #define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits 1560 #define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask 1561 #define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable 1562 1563 //***************************************************************************** 1564 // 1565 // The following are defines for the bit fields in the NVIC_MPU_BASE3 register. 1566 // 1567 //***************************************************************************** 1568 #define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask 1569 #define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid 1570 #define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number 1571 #define NVIC_MPU_BASE3_ADDR_S 5 1572 #define NVIC_MPU_BASE3_REGION_S 0 1573 1574 //***************************************************************************** 1575 // 1576 // The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. 1577 // 1578 //***************************************************************************** 1579 #define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable 1580 #define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege 1581 #define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask 1582 #define NVIC_MPU_ATTR3_SHAREABLE \ 1583 0x00040000 // Shareable 1584 #define NVIC_MPU_ATTR3_CACHEABLE \ 1585 0x00020000 // Cacheable 1586 #define NVIC_MPU_ATTR3_BUFFRABLE \ 1587 0x00010000 // Bufferable 1588 #define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits 1589 #define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask 1590 #define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable 1591 1592 //***************************************************************************** 1593 // 1594 // The following are defines for the bit fields in the NVIC_DBG_CTRL register. 1595 // 1596 //***************************************************************************** 1597 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask 1598 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key 1599 #define NVIC_DBG_CTRL_S_RESET_ST \ 1600 0x02000000 // Core has reset since last read 1601 #define NVIC_DBG_CTRL_S_RETIRE_ST \ 1602 0x01000000 // Core has executed insruction 1603 // since last read 1604 #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up 1605 #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping 1606 #define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt 1607 #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available 1608 #define NVIC_DBG_CTRL_C_SNAPSTALL \ 1609 0x00000020 // Breaks a stalled load/store 1610 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping 1611 #define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core 1612 #define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core 1613 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug 1614 1615 //***************************************************************************** 1616 // 1617 // The following are defines for the bit fields in the NVIC_DBG_XFER register. 1618 // 1619 //***************************************************************************** 1620 #define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read 1621 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register 1622 #define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 1623 #define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 1624 #define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 1625 #define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 1626 #define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 1627 #define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 1628 #define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 1629 #define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 1630 #define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 1631 #define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 1632 #define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 1633 #define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 1634 #define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 1635 #define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 1636 #define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 1637 #define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 1638 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register 1639 #define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP 1640 #define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP 1641 #define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP 1642 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask 1643 1644 //***************************************************************************** 1645 // 1646 // The following are defines for the bit fields in the NVIC_DBG_DATA register. 1647 // 1648 //***************************************************************************** 1649 #define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache 1650 #define NVIC_DBG_DATA_S 0 1651 1652 //***************************************************************************** 1653 // 1654 // The following are defines for the bit fields in the NVIC_DBG_INT register. 1655 // 1656 //***************************************************************************** 1657 #define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault 1658 #define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors 1659 #define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error 1660 #define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state 1661 #define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check 1662 #define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error 1663 #define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault 1664 #define NVIC_DBG_INT_RESET 0x00000008 // Core reset status 1665 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset 1666 #define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending 1667 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch 1668 1669 //***************************************************************************** 1670 // 1671 // The following are defines for the bit fields in the NVIC_SW_TRIG register. 1672 // 1673 //***************************************************************************** 1674 #define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID 1675 #define NVIC_SW_TRIG_INTID_S 0 1676 1677 //***************************************************************************** 1678 // 1679 // The following are defines for the bit fields in the NVIC_FPCC register. 1680 // 1681 //***************************************************************************** 1682 #define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation 1683 // Enable 1684 #define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable 1685 #define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready 1686 #define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready 1687 #define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready 1688 #define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready 1689 #define NVIC_FPCC_THREAD 0x00000008 // Thread Mode 1690 #define NVIC_FPCC_USER 0x00000002 // User Privilege Level 1691 #define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active 1692 1693 //***************************************************************************** 1694 // 1695 // The following are defines for the bit fields in the NVIC_FPCA register. 1696 // 1697 //***************************************************************************** 1698 #define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address 1699 #define NVIC_FPCA_ADDRESS_S 3 1700 1701 //***************************************************************************** 1702 // 1703 // The following are defines for the bit fields in the NVIC_FPDSC register. 1704 // 1705 //***************************************************************************** 1706 #define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default 1707 #define NVIC_FPDSC_DN 0x02000000 // DN Bit Default 1708 #define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default 1709 #define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default 1710 #define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode 1711 #define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) 1712 // mode 1713 #define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity 1714 // (RM) mode 1715 #define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode 1716 1717 #endif // __HW_NVIC_H__ 1718