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Searched refs:PPB_BASE (Results 1 – 9 of 9) sorted by relevance

/external/platform/pico/rp2_common/hardware_irq/
A Dirq.c56 return 0 != ((1u << num) & *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))); in irq_is_enabled()
63 *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = mask; in irq_set_mask_enabled()
64 *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)) = mask; in irq_set_mask_enabled()
66 *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICER_OFFSET)) = mask; in irq_set_mask_enabled()
72 *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num; in irq_set_pending()
381 io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u)); in irq_set_priority()
389 io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u)); in irq_get_priority()
431 io_rw_32 * p = (io_rw_32 *)(PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET); in irq_init_priorities()
/external/platform/pico/rp2040/hardware_structs/include/hardware/structs/
A Dsystick.h50 #define systick_hw ((systick_hw_t *)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET))
A Dmpu.h59 #define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
A Dscb.h67 #define scb_hw ((armv6m_scb_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET))
A Dnvic.h63 #define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))
/external/platform/pico/rp2_common/boot_stage2/asminclude/boot2_helpers/
A Dexit_from_boot2.S22 ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)
/external/platform/pico/rp2_common/hardware_irq/include/hardware/
A Dirq.h287 …*((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F… in irq_clear()
/external/platform/pico/rp2040/hardware_regs/include/hardware/regs/
A Daddressmap.h72 #define PPB_BASE _u(0xe0000000) macro
/external/platform/pico/rp2_common/pico_standard_link/
A Dcrt0.S205 ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)

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