| /external/arch/arm/arm-m/CMSIS/Include/ |
| A D | cachel1_armv7.h | 64 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ in SCB_EnableICache()
67 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
83 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
100 SCB->ICIALLU = 0UL; in SCB_InvalidateICache()
153 ccsidr = SCB->CCSIDR; in SCB_EnableDCache()
169 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
191 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ in SCB_DisableDCache()
194 ccsidr = SCB->CCSIDR; in SCB_DisableDCache()
229 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache()
264 ccsidr = SCB->CCSIDR; in SCB_CleanDCache()
[all …]
|
| A D | core_sc000.h | 668 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
872 … SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | in __NVIC_SetPriority()
896 …return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __… in __NVIC_GetPriority()
912 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_SetVector()
928 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_GetVector()
941 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in __NVIC_SystemReset()
|
| A D | core_cm0plus.h | 653 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
859 … SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | in __NVIC_SetPriority()
883 …return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __… in __NVIC_GetPriority()
953 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_SetVector()
974 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_GetVector()
991 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in __NVIC_SystemReset()
|
| A D | core_cm0.h | 539 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
741 … SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | in __NVIC_SetPriority()
765 …return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __… in __NVIC_GetPriority()
863 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in __NVIC_SystemReset()
|
| A D | core_cm1.h | 566 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
768 … SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | in __NVIC_SetPriority()
792 …return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __… in __NVIC_GetPriority()
890 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in __NVIC_SystemReset()
|
| A D | core_cm3.h | 1390 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
1482 …reg_value = SCB->AIRCR; /* read old register c… in __NVIC_SetPriorityGrouping()
1487 SCB->AIRCR = reg_value; in __NVIC_SetPriorityGrouping()
1498 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); in __NVIC_GetPriorityGrouping()
1646 …SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint… in __NVIC_SetPriority()
1669 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); in __NVIC_GetPriority()
1737 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_SetVector()
1753 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_GetVector()
1766 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in __NVIC_SystemReset()
1767 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | in __NVIC_SystemReset()
|
| A D | core_sc300.h | 1373 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
1465 …reg_value = SCB->AIRCR; /* read old register c… in __NVIC_SetPriorityGrouping()
1470 SCB->AIRCR = reg_value; in __NVIC_SetPriorityGrouping()
1481 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); in __NVIC_GetPriorityGrouping()
1629 …SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint… in __NVIC_SetPriority()
1652 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); in __NVIC_GetPriority()
1720 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_SetVector()
1736 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_GetVector()
1749 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in __NVIC_SystemReset()
1750 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | in __NVIC_SystemReset()
|
| A D | core_cm4.h | 1560 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
1658 …reg_value = SCB->AIRCR; /* read old register c… in __NVIC_SetPriorityGrouping()
1663 SCB->AIRCR = reg_value; in __NVIC_SetPriorityGrouping()
1674 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); in __NVIC_GetPriorityGrouping()
1822 …SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint… in __NVIC_SetPriority()
1845 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); in __NVIC_GetPriority()
1913 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_SetVector()
1929 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_GetVector()
1942 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in __NVIC_SystemReset()
1943 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | in __NVIC_SystemReset()
|
| A D | core_cm7.h | 1787 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
1885 …reg_value = SCB->AIRCR; /* read old register c… in __NVIC_SetPriorityGrouping()
1890 SCB->AIRCR = reg_value; in __NVIC_SetPriorityGrouping()
1901 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); in __NVIC_GetPriorityGrouping()
2049 …SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uin… in __NVIC_SetPriority()
2072 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); in __NVIC_GetPriority()
2140 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_SetVector()
2156 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_GetVector()
2169 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in __NVIC_SystemReset()
2170 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | in __NVIC_SystemReset()
[all …]
|
| /external/platform/stm32f0xx/STM32F0xx_HAL_Driver/inc/ |
| A D | stm32f0xx_ll_cortex.h | 194 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableSleep()
205 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep()
218 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit()
229 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_DisableSleepOnExit()
241 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend()
253 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_DisableEventOnPend()
271 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); in LL_CPUID_GetImplementer()
281 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); in LL_CPUID_GetVariant()
291 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); in LL_CPUID_GetArchitecture()
301 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); in LL_CPUID_GetParNo()
[all …]
|
| /external/platform/stm32f0xx/STM32F0xx_HAL_Driver/ |
| A D | stm32f0xx_hal_pwr.c | 292 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSLEEPMode()
349 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in HAL_PWR_EnterSTOPMode()
366 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTOPMode()
389 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in HAL_PWR_EnterSTANDBYMode()
410 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
423 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit()
437 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
450 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
|
| /external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Src/ |
| A D | stm32f7xx_hal_pwr.c | 408 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSLEEPMode()
461 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in HAL_PWR_EnterSTOPMode()
474 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTOPMode()
493 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in HAL_PWR_EnterSTANDBYMode()
542 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
554 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit()
566 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
578 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
|
| A D | stm32f7xx_hal_pwr_ex.c | 417 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in HAL_PWREx_EnterUnderDriveSTOPMode()
428 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in HAL_PWREx_EnterUnderDriveSTOPMode()
|
| /external/platform/stm32f1xx/STM32F10x_StdPeriph_Driver/src/ |
| A D | misc.c | 101 SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; in NVIC_PriorityGroupConfig()
123 tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; in NVIC_Init()
160 SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); in NVIC_SetVectorTable()
181 SCB->SCR |= LowPowerMode; in NVIC_SystemLPConfig()
185 SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); in NVIC_SystemLPConfig()
|
| A D | stm32f10x_pwr.c | 212 SCB->SCR |= SCB_SCR_SLEEPDEEP; in PWR_EnterSTOPMode()
227 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); in PWR_EnterSTOPMode()
242 SCB->SCR |= SCB_SCR_SLEEPDEEP; in PWR_EnterSTANDBYMode()
|
| /external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/src/ |
| A D | misc.c | 124 SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; in NVIC_PriorityGroupConfig()
148 tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; in NVIC_Init()
186 SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); in NVIC_SetVectorTable()
207 SCB->SCR |= LowPowerMode; in NVIC_SystemLPConfig()
211 SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); in NVIC_SystemLPConfig()
|
| A D | stm32f2xx_pwr.c | 486 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in PWR_EnterSTOPMode()
500 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in PWR_EnterSTOPMode()
523 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in PWR_EnterSTANDBYMode()
|
| A D | system_stm32f2xx.c | 239 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ in SystemInit()
241 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ in SystemInit()
|
| /external/platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/src/ |
| A D | misc.c | 117 SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; in NVIC_PriorityGroupConfig()
141 tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; in NVIC_Init()
179 SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); in NVIC_SetVectorTable()
200 SCB->SCR |= LowPowerMode; in NVIC_SystemLPConfig()
204 SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); in NVIC_SystemLPConfig()
|
| A D | stm32f4xx_pwr.c | 828 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in PWR_EnterSTOPMode()
842 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in PWR_EnterSTOPMode()
892 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in PWR_EnterUnderDriveSTOPMode()
906 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in PWR_EnterUnderDriveSTOPMode()
927 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in PWR_EnterSTANDBYMode()
|
| /external/platform/lpc15xx/lpcopen/lpc_chip_15xx/src/ |
| A D | pmu_15xx.c | 62 SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos); in Chip_PMU_DeepSleepState()
71 SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos); in Chip_PMU_PowerDownState()
81 SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos); in Chip_PMU_DeepPowerDownState()
|
| /external/platform/pico/rp2_common/cmsis/stub/CMSIS/Core/Include/ |
| A D | core_cm0plus.h | 653 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct… macro
859 … SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | in __NVIC_SetPriority()
883 …return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __… in __NVIC_GetPriority()
953 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_SetVector()
974 uint32_t *vectors = (uint32_t *)SCB->VTOR; in __NVIC_GetVector()
991 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | in __NVIC_SystemReset()
|
| A D | mpu_armv7.h | 196 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Enable()
208 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Disable()
|
| /external/platform/nrfx/mdk/ |
| A D | system_nrf5340_application.c | 230 SCB->NSACR |= (3UL << 10); in SystemInit()
237 SCB->CPACR |= (3UL << 20) | (3UL << 22); in SystemInit()
|
| A D | system_nrf9160.c | 223 SCB->NSACR |= (3UL << 10); in SystemInit()
230 SCB->CPACR |= (3UL << 20) | (3UL << 22); in SystemInit()
|