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Searched refs:SCB_SHCSR_MEMFAULTENA_Msk (Results 1 – 13 of 13) sorted by relevance

/external/arch/arm/arm-m/CMSIS/Include/
A Dmpu_armv8.h134 #ifdef SCB_SHCSR_MEMFAULTENA_Msk in ARM_MPU_Enable()
135 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Enable()
146 #ifdef SCB_SHCSR_MEMFAULTENA_Msk in ARM_MPU_Disable()
147 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Disable()
162 #ifdef SCB_SHCSR_MEMFAULTENA_Msk in ARM_MPU_Enable_NS()
163 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Enable_NS()
174 #ifdef SCB_SHCSR_MEMFAULTENA_Msk in ARM_MPU_Disable_NS()
175 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Disable_NS()
A Dmpu_armv7.h195 #ifdef SCB_SHCSR_MEMFAULTENA_Msk in ARM_MPU_Enable()
196 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Enable()
207 #ifdef SCB_SHCSR_MEMFAULTENA_Msk in ARM_MPU_Disable()
208 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Disable()
A Dcore_cm3.h522 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB … macro
A Dcore_sc300.h519 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB … macro
A Dcore_cm4.h580 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB … macro
A Dcore_cm7.h634 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB … macro
A Dcore_cm33.h694 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB … macro
A Dcore_cm35p.h694 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB … macro
A Dcore_armv8mml.h694 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB … macro
A Dcore_armv81mml.h714 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB … macro
A Dcore_cm55.h714 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB … macro
/external/platform/pico/rp2_common/cmsis/stub/CMSIS/Core/Include/
A Dmpu_armv7.h195 #ifdef SCB_SHCSR_MEMFAULTENA_Msk in ARM_MPU_Enable()
196 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Enable()
207 #ifdef SCB_SHCSR_MEMFAULTENA_Msk in ARM_MPU_Disable()
208 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in ARM_MPU_Disable()
/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Inc/
A Dstm32f7xx_hal_cortex.h443 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; in HAL_MPU_Disable()
466 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; in HAL_MPU_Enable()

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