| /external/platform/stm32f0xx/STM32F0xx_HAL_Driver/ |
| A D | stm32f0xx_hal_pwr.c | 292 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSLEEPMode()
349 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in HAL_PWR_EnterSTOPMode()
366 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTOPMode()
389 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in HAL_PWR_EnterSTANDBYMode()
410 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
423 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit()
437 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
450 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
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| /external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Src/ |
| A D | stm32f7xx_hal_pwr.c | 408 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSLEEPMode()
461 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in HAL_PWR_EnterSTOPMode()
474 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in HAL_PWR_EnterSTOPMode()
493 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in HAL_PWR_EnterSTANDBYMode()
542 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
554 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_DisableSleepOnExit()
566 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
578 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_DisableSEVOnPend()
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| A D | stm32f7xx_hal_pwr_ex.c | 417 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in HAL_PWREx_EnterUnderDriveSTOPMode()
428 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in HAL_PWREx_EnterUnderDriveSTOPMode()
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| /external/platform/stm32f0xx/STM32F0xx_HAL_Driver/inc/ |
| A D | stm32f0xx_ll_cortex.h | 194 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableSleep()
205 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in LL_LPM_EnableDeepSleep()
218 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_EnableSleepOnExit()
229 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in LL_LPM_DisableSleepOnExit()
241 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_EnableEventOnPend()
253 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in LL_LPM_DisableEventOnPend()
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| /external/platform/lpc15xx/lpcopen/lpc_chip_15xx/src/ |
| A D | pmu_15xx.c | 62 SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos); in Chip_PMU_DeepSleepState()
71 SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos); in Chip_PMU_PowerDownState()
81 SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos); in Chip_PMU_DeepPowerDownState()
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| /external/platform/stm32f1xx/STM32F10x_StdPeriph_Driver/src/ |
| A D | stm32f10x_pwr.c | 212 SCB->SCR |= SCB_SCR_SLEEPDEEP; in PWR_EnterSTOPMode()
227 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); in PWR_EnterSTOPMode()
242 SCB->SCR |= SCB_SCR_SLEEPDEEP; in PWR_EnterSTANDBYMode()
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| A D | misc.c | 181 SCB->SCR |= LowPowerMode; in NVIC_SystemLPConfig()
185 SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); in NVIC_SystemLPConfig()
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| /external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/src/ |
| A D | stm32f2xx_pwr.c | 486 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in PWR_EnterSTOPMode()
500 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in PWR_EnterSTOPMode()
523 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in PWR_EnterSTANDBYMode()
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| A D | misc.c | 207 SCB->SCR |= LowPowerMode; in NVIC_SystemLPConfig()
211 SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); in NVIC_SystemLPConfig()
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| /external/platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/src/ |
| A D | stm32f4xx_pwr.c | 828 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in PWR_EnterSTOPMode()
842 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in PWR_EnterSTOPMode()
892 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in PWR_EnterUnderDriveSTOPMode()
906 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); in PWR_EnterUnderDriveSTOPMode()
927 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in PWR_EnterSTANDBYMode()
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| A D | misc.c | 200 SCB->SCR |= LowPowerMode; in NVIC_SystemLPConfig()
204 SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); in NVIC_SystemLPConfig()
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| /external/arch/arm/arm-m/CMSIS/Include/ |
| A D | core_cm0.h | 347 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| A D | core_cm1.h | 347 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| A D | core_sc000.h | 358 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| A D | core_cm0plus.h | 365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| A D | core_cm3.h | 385 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| A D | core_sc300.h | 385 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| A D | core_cm4.h | 451 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| A D | core_armv8mbl.h | 393 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| A D | core_cm23.h | 393 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| A D | core_cm7.h | 466 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| A D | core_cm33.h | 510 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| A D | core_cm35p.h | 510 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| A D | core_armv8mml.h | 510 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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| /external/platform/pico/rp2_common/cmsis/stub/CMSIS/Core/Include/ |
| A D | core_cm0plus.h | 365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
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