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/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Inc/
A Dstm32f7xx_hal_cortex.h358 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ argument
359 ((STATE) == MPU_REGION_DISABLE))
361 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ argument
362 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
364 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ argument
365 ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
367 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ argument
368 ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
370 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ argument
371 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
A Dstm32f7xx_hal_dma.h701 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ argument
702 ((STATE) == DMA_PINC_DISABLE))
704 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ argument
705 ((STATE) == DMA_MINC_DISABLE))
724 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ argument
725 ((STATE) == DMA_FIFOMODE_ENABLE))
A Dstm32f7xx_hal_sai.h759 #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ argument
760 ((STATE) == SAI_SYNCEXT_IN_ENABLE) ||\
761 ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
762 ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
841 #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\ argument
842 ((STATE) == SAI_OUTPUT_RELEASED))
A Dstm32f7xx_hal_dac.h348 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ argument
349 ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
/external/platform/stm32f1xx/STM32F10x_StdPeriph_Driver/inc/
A Dstm32f10x_tim.h406 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ argument
418 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ argument
454 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ argument
506 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ argument
518 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ argument
530 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ argument
542 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ argument
875 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ argument
887 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ argument
900 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ argument
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A Dstm32f10x_fsmc.h340 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ argument
341 ((STATE) == FSMC_BurstAccessMode_Enable))
351 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ argument
352 ((STATE) == FSMC_AsynchronousWait_Enable))
553 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ argument
554 ((STATE) == FSMC_ECC_Enable))
A Dstm32f10x_dma.h125 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ argument
126 ((STATE) == DMA_PeripheralInc_Disable))
137 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ argument
138 ((STATE) == DMA_MemoryInc_Disable))
204 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) argument
A Dstm32f10x_flash.h86 #define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ argument
87 ((STATE) == FLASH_HalfCycleAccess_Disable))
98 #define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ argument
99 ((STATE) == FLASH_PrefetchBuffer_Disable))
A Dstm32f10x_dac.h185 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ argument
186 ((STATE) == DAC_OutputBuffer_Disable))
/external/platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/inc/
A Dstm32f4xx_tim.h354 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ argument
366 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ argument
402 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ argument
454 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ argument
466 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ argument
478 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ argument
490 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ argument
821 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ argument
833 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ argument
846 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ argument
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A Dstm32f4xx_fsmc.h329 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ argument
330 ((STATE) == FSMC_BurstAccessMode_Enable))
340 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ argument
341 ((STATE) == FSMC_AsynchronousWait_Enable))
513 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ argument
514 ((STATE) == FSMC_ECC_Enable))
A Dstm32f4xx_dma.h186 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ argument
187 ((STATE) == DMA_PeripheralInc_Disable))
199 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ argument
200 ((STATE) == DMA_MemoryInc_Disable))
272 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ argument
273 ((STATE) == DMA_FIFOMode_Enable))
A Dstm32f4xx_fmc.h447 #define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \ argument
448 ((STATE) == FMC_BurstAccessMode_Enable))
459 #define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \ argument
460 ((STATE) == FMC_AsynchronousWait_Enable))
665 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \ argument
666 ((STATE) == FMC_ECC_Enable))
A Dstm32f4xx_spdifrx.h156 #define IS_SPDIFRX_STATE(STATE) (((STATE) == SPDIFRX_STATE_IDLE) || \ argument
157 ((STATE) == SPDIFRX_STATE_SYNC) || \
158 ((STATE) == SPDIFRX_STATE_RCV))
A Dstm32f4xx_dfsdm.h148 #define IS_DFSDM_Redirection_STATE(STATE) (((STATE) == DFSDM_Redirection_Disabled) || \ argument
149 ((STATE) == DFSDM_Redirection_Enabled))
178 #define IS_DFSDM_CLK_DETECTOR_STATE(STATE) (((STATE) == DFSDM_CLKAbsenceDetector_Enable) || \ argument
179 ((STATE) == DFSDM_CLKAbsenceDetector_Disable))
190 #define IS_DFSDM_SC_DETECTOR_STATE(STATE) (((STATE) == DFSDM_ShortCircuitDetector_Enable) || \ argument
191 ((STATE) == DFSDM_ShortCircuitDetector_Disable))
A Dstm32f4xx_dac.h177 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ argument
178 ((STATE) == DAC_OutputBuffer_Disable))
/external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/inc/
A Dstm32f2xx_tim.h361 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ argument
373 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ argument
409 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ argument
461 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ argument
473 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ argument
485 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ argument
497 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ argument
828 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ argument
840 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ argument
853 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ argument
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A Dstm32f2xx_fsmc.h336 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ argument
337 ((STATE) == FSMC_BurstAccessMode_Enable))
347 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ argument
348 ((STATE) == FSMC_AsynchronousWait_Enable))
520 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ argument
521 ((STATE) == FSMC_ECC_Enable))
A Dstm32f2xx_dma.h193 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ argument
194 ((STATE) == DMA_PeripheralInc_Disable))
206 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ argument
207 ((STATE) == DMA_MemoryInc_Disable))
279 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ argument
280 ((STATE) == DMA_FIFOMode_Enable))
A Dstm32f2xx_dac.h184 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ argument
185 ((STATE) == DAC_OutputBuffer_Disable))
/external/platform/stm32f0xx/STM32F0xx_HAL_Driver/inc/
A Dstm32f0xx_hal_tim.h887 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ argument
888 ((STATE) == TIM_OCFAST_ENABLE))
896 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \ argument
899 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \ argument
986 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ argument
987 ((STATE) == TIM_OSSR_DISABLE))
989 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \ argument
990 ((STATE) == TIM_OSSI_DISABLE))
997 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \ argument
1003 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \ argument
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A Dstm32f0xx_hal_dma.h503 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ argument
504 ((STATE) == DMA_PINC_DISABLE))
506 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ argument
507 ((STATE) == DMA_MINC_DISABLE))
A Dstm32f0xx_hal_dac.h258 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ argument
259 ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/CMSIS/
A Dstm32f7xx.h142 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) argument
/external/platform/stm32f0xx/CMSIS/inc/
A Dstm32f0xx.h194 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) argument

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