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Searched refs:TER (Results 1 – 9 of 9) sorted by relevance

/external/arch/arm/arm-m/CMSIS/Include/
A Dcore_cm3.h767 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
1881 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
A Dcore_sc300.h752 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
1855 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
A Dcore_cm4.h825 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
2067 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
A Dcore_cm7.h1049 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
2304 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
A Dcore_cm33.h1023 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
3203 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
A Dcore_cm35p.h1023 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
3203 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
A Dcore_armv8mml.h1023 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
3135 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
A Dcore_armv81mml.h1084 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
4154 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()
A Dcore_cm55.h1084 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ member
4215 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ in ITM_SendChar()

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