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Searched refs:U (Results 1 – 25 of 137) sorted by relevance

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/external/arch/arm/arm-m/CMSIS/Include/
A Dcore_cm7.h82 #define __FPU_USED 0U
85 #define __FPU_USED 0U
94 #define __FPU_USED 0U
97 #define __FPU_USED 0U
106 #define __FPU_USED 0U
109 #define __FPU_USED 0U
118 #define __FPU_USED 0U
121 #define __FPU_USED 0U
1938 return(0U); in __NVIC_GetEnableIRQ()
1976 return(0U); in __NVIC_GetPendingIRQ()
[all …]
A Dcore_cm4.h82 #define __FPU_USED 0U
85 #define __FPU_USED 0U
94 #define __FPU_USED 0U
97 #define __FPU_USED 0U
106 #define __FPU_USED 0U
109 #define __FPU_USED 0U
118 #define __FPU_USED 0U
121 #define __FPU_USED 0U
1711 return(0U); in __NVIC_GetEnableIRQ()
1749 return(0U); in __NVIC_GetPendingIRQ()
[all …]
A Dcore_cm33.h84 #define __FPU_USED 0U
87 #define __FPU_USED 0U
2405 return(0U); in __NVIC_GetEnableIRQ()
2443 return(0U); in __NVIC_GetPendingIRQ()
2494 return(0U); in __NVIC_GetActive()
2516 return(0U); in NVIC_GetTargetState()
2538 return(0U); in NVIC_SetTargetState()
2560 return(0U); in NVIC_ClearTargetState()
2780 return(0U); in TZ_NVIC_GetEnableIRQ_NS()
2816 return(0U); in TZ_NVIC_GetPendingIRQ_NS()
[all …]
A Dcore_cm35p.h84 #define __FPU_USED 0U
87 #define __FPU_USED 0U
2405 return(0U); in __NVIC_GetEnableIRQ()
2443 return(0U); in __NVIC_GetPendingIRQ()
2494 return(0U); in __NVIC_GetActive()
2516 return(0U); in NVIC_GetTargetState()
2538 return(0U); in NVIC_SetTargetState()
2560 return(0U); in NVIC_ClearTargetState()
2780 return(0U); in TZ_NVIC_GetEnableIRQ_NS()
2816 return(0U); in TZ_NVIC_GetPendingIRQ_NS()
[all …]
A Dcore_armv8mml.h84 #define __FPU_USED 0U
87 #define __FPU_USED 0U
2330 return(0U); in __NVIC_GetEnableIRQ()
2368 return(0U); in __NVIC_GetPendingIRQ()
2419 return(0U); in __NVIC_GetActive()
2441 return(0U); in NVIC_GetTargetState()
2463 return(0U); in NVIC_SetTargetState()
2485 return(0U); in NVIC_ClearTargetState()
2705 return(0U); in TZ_NVIC_GetEnableIRQ_NS()
2741 return(0U); in TZ_NVIC_GetPendingIRQ_NS()
[all …]
A Dcore_cm3.h76 #define __FPU_USED 0U
141 #define __MPU_PRESENT 0U
156 #define __Vendor_SysTickConfig 0U
256 #define IPSR_ISR_Pos 0U /*!< IPSR…
1535 return(0U); in __NVIC_GetEnableIRQ()
1573 return(0U); in __NVIC_GetPendingIRQ()
1624 return(0U); in __NVIC_GetActive()
1807 return 0U; /* No FPU */ in SCB_GetFPUType()
1823 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1883 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
[all …]
A Dcore_sc300.h76 #define __FPU_USED 0U
141 #define __MPU_PRESENT 0U
156 #define __Vendor_SysTickConfig 0U
256 #define IPSR_ISR_Pos 0U /*!< IPSR…
1518 return(0U); in __NVIC_GetEnableIRQ()
1556 return(0U); in __NVIC_GetPendingIRQ()
1607 return(0U); in __NVIC_GetActive()
1781 return 0U; /* No FPU */ in SCB_GetFPUType()
1797 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1857 while (ITM->PORT[0U].u32 == 0UL) in ITM_SendChar()
[all …]
A Dcore_cm23.h78 #define __FPU_USED 0U
143 #define __FPU_PRESENT 0U
1551 return(0U); in __NVIC_GetEnableIRQ()
1589 return(0U); in __NVIC_GetPendingIRQ()
1640 return(0U); in __NVIC_GetActive()
1662 return(0U); in NVIC_GetTargetState()
1684 return(0U); in NVIC_SetTargetState()
1706 return(0U); in NVIC_ClearTargetState()
1902 return(0U); in TZ_NVIC_GetEnableIRQ_NS()
1938 return(0U); in TZ_NVIC_GetPendingIRQ_NS()
[all …]
A Dcore_cm55.h214 #if __FPU_PRESENT != 0U
3342 return(0U); in __NVIC_GetEnableIRQ()
3380 return(0U); in __NVIC_GetPendingIRQ()
3431 return(0U); in __NVIC_GetActive()
3453 return(0U); in NVIC_GetTargetState()
3475 return(0U); in NVIC_SetTargetState()
3497 return(0U); in NVIC_ClearTargetState()
3717 return(0U); in TZ_NVIC_GetEnableIRQ_NS()
3753 return(0U); in TZ_NVIC_GetPendingIRQ_NS()
3804 return(0U); in TZ_NVIC_GetActive_NS()
[all …]
A Dcore_armv81mml.h214 #if __FPU_PRESENT != 0U
3305 return(0U); in __NVIC_GetEnableIRQ()
3343 return(0U); in __NVIC_GetPendingIRQ()
3394 return(0U); in __NVIC_GetActive()
3416 return(0U); in NVIC_GetTargetState()
3438 return(0U); in NVIC_SetTargetState()
3460 return(0U); in NVIC_ClearTargetState()
3680 return(0U); in TZ_NVIC_GetEnableIRQ_NS()
3716 return(0U); in TZ_NVIC_GetPendingIRQ_NS()
3767 return(0U); in TZ_NVIC_GetActive_NS()
[all …]
A Dcore_cm0plus.h76 #define __FPU_USED 0U
141 #define __MPU_PRESENT 0U
146 #define __VTOR_PRESENT 0U
156 #define __Vendor_SysTickConfig 0U
733 #define __NVIC_GetPriorityGrouping() (0U)
746 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
768 return(0U); in __NVIC_GetEnableIRQ()
783 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
806 return(0U); in __NVIC_GetPendingIRQ()
821 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_SetPendingIRQ()
[all …]
A Dcore_sc000.h76 #define __FPU_USED 0U
141 #define __MPU_PRESENT 0U
146 #define __VTOR_PRESENT 0U
156 #define __Vendor_SysTickConfig 0U
759 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
781 return(0U); in __NVIC_GetEnableIRQ()
796 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
819 return(0U); in __NVIC_GetPendingIRQ()
834 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_SetPendingIRQ()
849 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_ClearPendingIRQ()
[all …]
A Dcore_armv8mbl.h78 #define __FPU_USED 0U
143 #define __FPU_PRESENT 0U
1476 return(0U); in __NVIC_GetEnableIRQ()
1514 return(0U); in __NVIC_GetPendingIRQ()
1565 return(0U); in __NVIC_GetActive()
1587 return(0U); in NVIC_GetTargetState()
1609 return(0U); in NVIC_SetTargetState()
1631 return(0U); in NVIC_ClearTargetState()
1827 return(0U); in TZ_NVIC_GetEnableIRQ_NS()
1863 return(0U); in TZ_NVIC_GetPendingIRQ_NS()
[all …]
A Dcachel1_armv7.h150 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()
165 } while (ways-- != 0U); in SCB_EnableDCache()
166 } while(sets-- != 0U); in SCB_EnableDCache()
206 } while (ways-- != 0U); in SCB_DisableDCache()
207 } while(sets-- != 0U); in SCB_DisableDCache()
241 } while (ways-- != 0U); in SCB_InvalidateDCache()
242 } while(sets-- != 0U); in SCB_InvalidateDCache()
276 } while (ways-- != 0U); in SCB_CleanDCache()
277 } while(sets-- != 0U); in SCB_CleanDCache()
311 } while (ways-- != 0U); in SCB_CleanInvalidateDCache()
[all …]
A Dcore_cm0.h76 #define __FPU_USED 0U
146 #define __Vendor_SysTickConfig 0U
615 #define __NVIC_GetPriorityGrouping() (0U)
628 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
650 return(0U); in __NVIC_GetEnableIRQ()
665 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
688 return(0U); in __NVIC_GetPendingIRQ()
703 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_SetPendingIRQ()
718 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_ClearPendingIRQ()
894 return 0U; /* No FPU */ in SCB_GetFPUType()
[all …]
A Dmpu_armv7.h63 #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
133 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
144 …EVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, …
162 #define ARM_MPU_CACHEP_NOCACHE 0U
221 MPU->RASR = 0U; in ARM_MPU_ClrRegion()
254 for (i = 0U; i < len; ++i) in ARM_MPU_OrderedMemcpy()
A Dcore_cm1.h76 #define __FPU_USED 0U
146 #define __Vendor_SysTickConfig 0U
642 #define __NVIC_GetPriorityGrouping() (0U)
655 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
677 return(0U); in __NVIC_GetEnableIRQ()
692 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
715 return(0U); in __NVIC_GetPendingIRQ()
730 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_SetPendingIRQ()
745 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_ClearPendingIRQ()
921 return 0U; /* No FPU */ in SCB_GetFPUType()
[all …]
/external/platform/stm32f0xx/STM32F0xx_HAL_Driver/
A Dstm32f0xx_hal_can.c791 uint32_t status = 0U; in HAL_CAN_IsSleepActive()
844 if (((tsr & CAN_TSR_TME0) != 0U) || in HAL_CAN_AddTxMessage()
845 ((tsr & CAN_TSR_TME1) != 0U) || in HAL_CAN_AddTxMessage()
846 ((tsr & CAN_TSR_TME2) != 0U)) in HAL_CAN_AddTxMessage()
979 uint32_t freelevel = 0U; in HAL_CAN_GetTxMailboxesFreeLevel()
1022 uint32_t status = 0U; in HAL_CAN_IsTxMessagePending()
1054 uint32_t timestamp = 0U; in HAL_CAN_GetTxTimestamp()
1068 transmitmailbox = 0U; in HAL_CAN_GetTxTimestamp()
1190 uint32_t filllevel = 0U; in HAL_CAN_GetRxFifoFillLevel()
1513 if ((msrflags & CAN_MSR_WKUI) != 0U) in HAL_CAN_IRQHandler()
[all …]
A Dstm32f0xx_hal_spi.c217 #if (USE_SPI_CRC != 0U)
306 #if (USE_SPI_CRC != 0U) in HAL_SPI_Init()
368 #if (USE_SPI_CRC != 0U) in HAL_SPI_Init()
380 #if (USE_SPI_CRC != 0U) in HAL_SPI_Init()
565 #if (USE_SPI_CRC != 0U) in HAL_SPI_Transmit()
657 #if (USE_SPI_CRC != 0U) in HAL_SPI_Transmit()
939 uint32_t tmp = 0U, tmp1 = 0U; in HAL_SPI_TransmitReceive()
1036 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) in HAL_SPI_TransmitReceive()
1094 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) in HAL_SPI_TransmitReceive()
1438 uint32_t tmp = 0U, tmp1 = 0U; in HAL_SPI_TransmitReceive_IT()
[all …]
A Dstm32f0xx_hal_pcd.c138 uint32_t i = 0U; in HAL_PCD_Init()
632 if(address == 0U) in HAL_PCD_SetAddress()
724 if (ep->is_in==0U) in HAL_PCD_EP_Open()
795 if (ep->is_in==0U) in HAL_PCD_EP_Close()
843 ep->is_in = 0U; in HAL_PCD_EP_Receive()
855 ep->xfer_len =0U; in HAL_PCD_EP_Receive()
916 ep->xfer_len =0U; in HAL_PCD_EP_Transmit()
975 if (ep->num == 0U) in HAL_PCD_EP_SetStall()
1015 ep->is_stall = 0U; in HAL_PCD_EP_ClrStall()
1191 uint16_t count=0U; in PCD_EP_ISR_Handler()
[all …]
A Dstm32f0xx_hal_timebase_rtc_alarm_template.c89 #define RTC_ASYNCH_PREDIV 0U
92 #define RTC_ASYNCH_PREDIV 0U
114 __IO uint32_t counter = 0U; in HAL_InitTick()
178 counter = 0U; in HAL_InitTick()
204 counter = 0U; in HAL_InitTick()
213 hRTC_Handle.Instance->DR = 0U; in HAL_InitTick()
214 hRTC_Handle.Instance->TR = 0U; in HAL_InitTick()
221 HAL_NVIC_SetPriority(RTC_IRQn, TickPriority, 0U); in HAL_InitTick()
271 __IO uint32_t counter = 0U; in HAL_RTC_AlarmAEventCallback()
288 hrtc->Instance->DR = 0U; in HAL_RTC_AlarmAEventCallback()
[all …]
A Dstm32f0xx_hal_usart.c491 uint16_t* tmp=0U; in HAL_USART_Transmit()
578 uint16_t* tmp=0U; in HAL_USART_Receive()
678 uint16_t* tmp=0U; in HAL_USART_TransmitReceive()
694 if(((((uint32_t)pTxData)&1U) != 0U) || ((((uint32_t)pRxData)&1U) != 0U)) in HAL_USART_TransmitReceive()
931 if(((((uint32_t)pTxData)&1U) != 0U) || ((((uint32_t)pRxData)&1U) != 0U)) in HAL_USART_TransmitReceive_IT()
986 uint32_t *tmp=0U; in HAL_USART_Transmit_DMA()
1492 abortcplt = 0U; in HAL_USART_Abort_IT()
1516 abortcplt = 0U; in HAL_USART_Abort_IT()
2309 uint16_t* tmp=0U; in USART_Transmit_IT()
2382 uint16_t* tmp=0U; in USART_Receive_IT()
[all …]
A Dstm32f0xx_hal_crc.c298 uint32_t index = 0U; /* CRC input data buffer index */ in HAL_CRC_Accumulate()
299 uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ in HAL_CRC_Accumulate()
311 for(index = 0U; index < BufferLength; index++) in HAL_CRC_Accumulate()
358 uint32_t index = 0U; /* CRC input data buffer index */ in HAL_CRC_Calculate()
375 for(index = 0U; index < BufferLength; index++) in HAL_CRC_Calculate()
457 uint32_t i = 0U; /* input data buffer index */ in CRC_Handle_8()
462 for(i = 0U; i < (BufferLength/4U); i++) in CRC_Handle_8()
467 if ((BufferLength%4U) != 0U) in CRC_Handle_8()
500 uint32_t i = 0U; /* input data buffer index */ in CRC_Handle_16()
505 for(i = 0U; i < (BufferLength/2U); i++) in CRC_Handle_16()
[all …]
/external/platform/pico/rp2_common/cmsis/stub/CMSIS/Core/Include/
A Dcore_cm0plus.h76 #define __FPU_USED 0U
141 #define __MPU_PRESENT 0U
146 #define __VTOR_PRESENT 0U
156 #define __Vendor_SysTickConfig 0U
733 #define __NVIC_GetPriorityGrouping() (0U)
746 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_EnableIRQ()
768 return(0U); in __NVIC_GetEnableIRQ()
783 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_DisableIRQ()
806 return(0U); in __NVIC_GetPendingIRQ()
821 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); in __NVIC_SetPendingIRQ()
[all …]
A Dmpu_armv7.h63 #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
133 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
144 …EVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, …
162 #define ARM_MPU_CACHEP_NOCACHE 0U
221 MPU->RASR = 0U; in ARM_MPU_ClrRegion()
254 for (i = 0U; i < len; ++i) in ARM_MPU_OrderedMemcpy()

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