Searched refs:XIP_SSI_BASE (Results 1 – 7 of 7) sorted by relevance
| /external/platform/pico/rp2_common/boot_stage2/ |
| A D | boot2_w25x10cl.S | 82 ldr r3, =XIP_SSI_BASE // Use as base address where possible
127 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
176 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
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| A D | boot2_is25lp080.S | 89 ldr r3, =XIP_SSI_BASE // Use as base address where possible
192 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
235 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
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| A D | boot2_generic_03h.S | 63 ldr r3, =XIP_SSI_BASE // Use as base address where possible
77 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
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| A D | boot2_at25sf128a.S | 116 ldr r3, =XIP_SSI_BASE
221 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
258 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
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| A D | boot2_w25q080.S | 116 ldr r3, =XIP_SSI_BASE
223 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
260 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
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| /external/platform/pico/rp2040/hardware_regs/include/hardware/regs/ |
| A D | addressmap.h | 26 #define XIP_SSI_BASE _u(0x18000000) macro
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| /external/platform/pico/rp2040/hardware_structs/include/hardware/structs/ |
| A D | ssi.h | 208 #define ssi_hw ((ssi_hw_t *)XIP_SSI_BASE)
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