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/external/platform/nrf51/include/platform/
A Dnrf518xx.h220 __I uint32_t RESERVED8;
254 __I uint32_t RESERVED1;
263 __I uint32_t RESERVED4;
351 __I uint32_t RESERVED5;
374 __I uint32_t RESERVED7;
416 __I uint32_t RESERVED3;
429 __I uint32_t RESERVED9;
464 __I uint32_t RESERVED3;
468 __I uint32_t RESERVED4;
471 __I uint32_t RESERVED5;
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/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/inc/
A Dsysctl_15xx.h49 __I uint32_t RESERVED0[2];
53 __I uint32_t RESERVED1[1];
55 __I uint32_t RESERVED2[8];
59 __I uint32_t RESERVED3[10];
64 __I uint32_t RESERVED4[1];
66 __I uint32_t RESERVED5[1];
70 __I uint32_t RESERVED6[5];
77 __I uint32_t RESERVED7[4];
80 __I uint32_t RESERVED8[1];
82 __I uint32_t RESERVED9[9];
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A Ddma_15xx.h49 __I uint32_t RESERVED0;
51 __I uint32_t RESERVED1;
53 __I uint32_t RESERVED2;
55 __I uint32_t RESERVED3;
57 __I uint32_t RESERVED4;
59 __I uint32_t RESERVED5;
61 __I uint32_t RESERVED6;
63 __I uint32_t RESERVED7;
65 __I uint32_t RESERVED8;
67 __I uint32_t RESERVED9;
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A Dinmux_15xx.h49 __I uint32_t RESERVED1[1];
51 __I uint32_t RESERVED2[1];
53 __I uint32_t RESERVED3[5];
55 __I uint32_t RESERVED4[5];
56 __I uint32_t RESERVED4A[16];
59 __I uint32_t RESERVED5[6];
61 __I uint32_t RESERVED6[4];
A Di2c_common_15xx.h54 __I uint32_t INTSTAT; /*!< I2C Interrupt Status Register */
55 __I uint32_t RESERVED0;
59 __I uint32_t RESERVED1[5];
64 __I uint32_t RESERVED2[9];
65 __I uint32_t MONRXDAT; /*!< I2C Monitor Data Register */
A Dfmc_15xx.h48 __I uint32_t RESERVED1[7];
51 __I uint32_t RESERVED2;
52 __I uint32_t FMSW[1];
A Dusbd_15xx.h60 __I uint32_t RESERVED0[1];
61 __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
A Dsctipu_15xx.h50 __I uint32_t RESERVED[6];
58 __I uint32_t RESERVED[7];
A Duart_15xx.h55 __I uint32_t RXDATA; /*!< Receive Data register */
56 __I uint32_t RXDATA_STAT; /*!< Receive Data with status register */
A Dadc_15xx.h59 __I uint32_t RESERVED1[2];
60__I uint32_t DR[12]; /*!< A/D Channel Data Register. This register contains the result of th…
A Dwwdt_15xx.h51__I uint32_t TV; /*!< Watchdog timer value register. This register reads out the current value…
A Dritimer_15xx.h54 __I uint32_t RESERVED0[1];
A Dspi_15xx.h52 __I uint32_t RXDAT; /*!< SPI Receive Data register*/
57 __I uint32_t INTSTAT; /*!< SPI Interrupt Status register*/
A Dcrc_15xx.h51 __I uint32_t SUM; /*!< CRC Checksum Register. */
A Dgpiogroup_15xx.h49 __I uint32_t RESERVED0[7];
A Dswm_15xx.h49 __I uint32_t RESERVED0[96];
/external/platform/pico/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/
A DRP2040.h96 #define __IM __I
/external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/src/
A Dsystem_stm32f2xx.c178 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/external/arch/arm/arm-m/CMSIS/Include/
A Dcore_cm0.h160 #define __I volatile /*!< Defines 'read only' permissions */ macro
162 #define __I volatile const /*!< Defines 'read only' permissions */
A Dcore_cm1.h160 #define __I volatile /*!< Defines 'read only' permissions */ macro
162 #define __I volatile const /*!< Defines 'read only' permissions */
A Dcore_sc000.h170 #define __I volatile /*!< Defines 'read only' permissions */ macro
172 #define __I volatile const /*!< Defines 'read only' permissions */
A Dcore_cm0plus.h170 #define __I volatile /*!< Defines 'read only' permissions */ macro
172 #define __I volatile const /*!< Defines 'read only' permissions */
/external/platform/pico/rp2_common/cmsis/stub/CMSIS/Core/Include/
A Dcore_cm0plus.h170 #define __I volatile /*!< Defines 'read only' permissions */ macro
172 #define __I volatile const /*!< Defines 'read only' permissions */
/external/platform/stm32f1xx/STM32F10x_StdPeriph_Driver/src/
A Dstm32f10x_rcc.c192 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
193 static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
/external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/CMSIS/
A Dstm32f2xx.h269 typedef __I int32_t vsc32; /*!< Read Only */
270 typedef __I int16_t vsc16; /*!< Read Only */
271 typedef __I int8_t vsc8; /*!< Read Only */
285 typedef __I uint32_t vuc32; /*!< Read Only */
286 typedef __I uint16_t vuc16; /*!< Read Only */
287 typedef __I uint8_t vuc8; /*!< Read Only */
829 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
830 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
831 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
832 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
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