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Searched refs:__IM (Results 1 – 25 of 28) sorted by relevance

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/external/platform/nrfx/mdk/
A Dnrf51.h127 #define __IM __I macro
233 __IM uint32_t RESERVED8;
268 __IM uint32_t RESERVED1;
277 __IM uint32_t RESERVED4;
358 __IM uint32_t RESERVED5;
381 __IM uint32_t RESERVED7;
424 __IM uint32_t RESERVED3;
438 __IM uint32_t RESERVED9;
476 __IM uint32_t RESERVED3;
504 __IM uint32_t RESERVED;
[all …]
A Dnrf5340_network.h119 #define __IM __I macro
173 __IM uint32_t RESERVED;
437 __IM uint32_t RESERVED;
450 __IM uint32_t RESERVED;
536 __IM uint32_t RESERVED3;
635 __IM uint32_t RESERVED7;
784 __IM uint32_t RESERVED3;
819 __IM uint32_t RESERVED7;
1133 __IM uint32_t RESERVED;
1528 __IM uint32_t RESERVED;
[all …]
A Dnrf52811.h135 #define __IM __I macro
229 __IM uint32_t RESERVED;
665 __IM uint32_t RESERVED1;
675 __IM uint32_t RESERVED4;
796 __IM uint32_t RESERVED2;
825 __IM uint32_t RESERVED7;
913 __IM uint32_t RESERVED3;
1136 __IM uint32_t RESERVED;
1189 __IM uint32_t RESERVED;
1562 __IM uint32_t RESERVED;
[all …]
A Dnrf52805.h132 #define __IM __I macro
226 __IM uint32_t RESERVED;
598 __IM uint32_t RESERVED1;
608 __IM uint32_t RESERVED4;
723 __IM uint32_t RESERVED2;
741 __IM uint32_t RESERVED8;
806 __IM uint32_t RESERVED3;
819 __IM uint32_t RESERVED9;
903 __IM uint32_t RESERVED;
956 __IM uint32_t RESERVED;
[all …]
A Dnrf52820.h134 #define __IM __I macro
223 __IM uint32_t RESERVED;
456 __IM uint32_t RESERVED;
493 __IM uint32_t RESERVED;
625 __IM uint32_t RESERVED3;
655 __IM uint32_t RESERVED1;
670 __IM uint32_t RESERVED5;
806 __IM uint32_t RESERVED2;
1149 __IM uint32_t RESERVED;
1202 __IM uint32_t RESERVED;
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A Dnrf52.h145 #define __IM __I macro
256 __IM uint32_t RESERVED;
628 __IM uint32_t RESERVED;
745 __IM uint32_t RESERVED;
849 __IM uint32_t RESERVED1;
859 __IM uint32_t RESERVED4;
908 __IM uint32_t RESERVED2;
1177 __IM uint32_t RESERVED;
1322 __IM uint32_t RESERVED;
1760 __IM uint32_t RESERVED;
[all …]
A Dnrf52810.h135 #define __IM __I macro
229 __IM uint32_t RESERVED;
646 __IM uint32_t RESERVED1;
656 __IM uint32_t RESERVED4;
771 __IM uint32_t RESERVED2;
781 __IM uint32_t RESERVED6;
801 __IM uint32_t RESERVED8;
942 __IM uint32_t RESERVED;
995 __IM uint32_t RESERVED;
1494 __IM uint32_t RESERVED;
[all …]
A Dnrf52840.h151 #define __IM __I macro
274 __IM uint32_t RESERVED;
609 __IM uint32_t RESERVED;
694 __IM uint32_t RESERVED;
758 __IM uint32_t RESERVED;
857 __IM uint32_t RESERVED;
967 __IM uint32_t RESERVED1;
982 __IM uint32_t RESERVED5;
1457 __IM uint32_t RESERVED;
1510 __IM uint32_t RESERVED;
[all …]
A Dnrf5340_application.h140 #define __IM __I macro
456 __IM uint32_t RESERVED;
482 __IM uint32_t RESERVED;
908 __IM uint32_t RESERVED;
989 __IM uint32_t RESERVED;
1062 __IM uint32_t RESERVED;
1151 __IM uint32_t RESERVED1;
1221 __IM uint32_t RESERVED;
1425 __IM uint32_t RESERVED;
1723 __IM uint32_t RESERVED;
[all …]
A Dnrf52833.h149 #define __IM __I macro
257 __IM uint32_t RESERVED;
611 __IM uint32_t RESERVED;
696 __IM uint32_t RESERVED;
760 __IM uint32_t RESERVED;
925 __IM uint32_t RESERVED1;
940 __IM uint32_t RESERVED5;
1431 __IM uint32_t RESERVED;
1484 __IM uint32_t RESERVED;
1950 __IM uint32_t RESERVED;
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A Dnrf9160.h142 #define __IM __I macro
166 __IM uint32_t RESERVED;
692 __IM uint32_t RESERVED;
743 __IM uint32_t RESERVED1;
878 __IM uint32_t RESERVED5;
967 __IM uint32_t RESERVED1;
973 __IM uint32_t RESERVED3;
980 __IM uint32_t RESERVED6;
1085 __IM uint32_t RESERVED;
1620 __IM uint32_t RESERVED;
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/external/arch/arm/arm-m/CMSIS/Include/
A Dcore_cm7.h462 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
477 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
484 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1155 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1291 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1293 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1295 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1302 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1303 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm4.h230 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
447 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
462 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
1064 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1065 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1066 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1068 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1069 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1075 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1076 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm3.h178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
396 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
1006 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1007 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1008 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1010 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1011 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1017 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1018 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_sc300.h178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
396 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
991 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
992 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
993 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
995 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
996 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1002 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1003 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
[all …]
A Dcore_cm33.h286 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
506 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
521 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
525 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
526 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
527 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1031 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1188 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1313 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1476 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
[all …]
A Dcore_cm35p.h286 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
506 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
521 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
525 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
526 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
527 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1031 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1188 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1313 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1476 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
[all …]
A Dcore_armv8mml.h286 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
506 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
521 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
525 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
526 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
527 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1031 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1188 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1317 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
1401 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
[all …]
A Dcore_armv81mml.h293 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
513 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
528 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
532 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
533 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
534 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1092 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1250 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1379 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
2279 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
[all …]
A Dcore_cm55.h293 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
513 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
528 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
532 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
533 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
534 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
1092 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1250 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1413 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
2314 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
[all …]
A Dcore_cm23.h201 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
385 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
565 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
616 …__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
740 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
751 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
752 …__IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
903 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1011 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1284 …__IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register …
[all …]
A Dcore_armv8mbl.h201 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
385 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
565 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
616 …__IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
741 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
743 __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
744 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
828 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
936 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1209 …__IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register …
[all …]
A Dcore_sc000.h178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
354 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
493 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
542 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
A Dcore_cm0plus.h178 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro
357 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
477 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
526 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
/external/platform/pico/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/
A DRP2040.h95 #ifndef __IM /*!< Fallback for older CMSIS versions …
96 #define __IM __I macro

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