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Searched refs:__IO (Results 1 – 25 of 247) sorted by relevance

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/external/platform/nrf51/include/platform/
A Dnrf518xx.h218 …__IO uint32_t GPREGRET; /*!< General purpose retention register. This re…
223 …__IO uint32_t RESET; /*!< Pin reset functionality configuration regis…
340 …__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength com…
712 …__IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (…
745 …__IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading o…
747 …__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading …
751 …__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (327…
828 …__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB …
869 …__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for t…
908 …__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for t…
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/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Inc/
A Dstm32f7xx_hal_sd.h105 __IO uint8_t CSDStruct; /*!< CSD structure */
152 __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
153 __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
154 __IO uint32_t ProdName1; /*!< Product Name part1 */
155 __IO uint8_t ProdName2; /*!< Product Name part2 */
156 __IO uint8_t ProdRev; /*!< Product Revision */
157 __IO uint32_t ProdSN; /*!< Product Serial Number */
158 __IO uint8_t Reserved1; /*!< Reserved1 */
159 __IO uint16_t ManufactDate; /*!< Manufacturing Date */
160 __IO uint8_t CID_CRC; /*!< CID CRC */
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/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/inc/
A Dsysctl_15xx.h50 __IO uint32_t AHBBUFEN0;
51 __IO uint32_t AHBBUFEN1;
54 __IO uint32_t NMISRC; /*!< NMI source control register */
73 __IO uint32_t SYSTICKCLKDIV; /*!< SYSTICK clock divider */
81 __IO uint32_t CLKOUTDIV; /*!< Clock out divider register */
83 __IO uint32_t FREQMECTRL; /*!< Frequency measure register */
84 __IO uint32_t FLASHCFG; /*!< Flash configuration register */
89 __IO uint32_t BODCTRL; /*!< Brown Out Detect register */
97 __IO uint32_t USBPLLCTRL; /*!< USB PLL control register */
99 __IO uint32_t SCTPLLCTRL; /*!< SCT PLL control register */
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A Dusbd_15xx.h48 __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
49 __IO uint32_t _INFO; /*!< USB Info register */
50 __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
51 __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
52 __IO uint32_t LPM; /*!< Link Power Management register */
53 __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
54 __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
56 __IO uint32_t INTSTAT; /*!< USB interrupt status register */
57 __IO uint32_t INTEN; /*!< USB interrupt enable register */
58 __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
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A Di2c_common_15xx.h48 __IO uint32_t CFG; /*!< I2C Configuration Register common for Master, Slave and Monitor */
49 __IO uint32_t STAT; /*!< I2C Status Register common for Master, Slave and Monitor */
52 __IO uint32_t TIMEOUT; /*!< I2C Timeout value Register */
53 __IO uint32_t CLKDIV; /*!< I2C Clock Divider Register */
56 __IO uint32_t MSTCTL; /*!< I2C Master Control Register */
57 __IO uint32_t MSTTIME; /*!< I2C Master Time Register for SCL */
58 __IO uint32_t MSTDAT; /*!< I2C Master Data Register */
60 __IO uint32_t SLVCTL; /*!< I2C Slave Control Register */
61 __IO uint32_t SLVDAT; /*!< I2C Slave Data Register */
62 __IO uint32_t SLVADR[4]; /*!< I2C Slave Address Registers */
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A Dpinint_15xx.h48 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
49 __IO uint32_t IENR; /*!< Pin Interrupt Enable (Rising) register */
50 __IO uint32_t SIENR; /*!< Set Pin Interrupt Enable (Rising) register */
51 __IO uint32_t CIENR; /*!< Clear Pin Interrupt Enable (Rising) register */
52 __IO uint32_t IENF; /*!< Pin Interrupt Enable Falling Edge / Active Level register */
53 __IO uint32_t SIENF; /*!< Set Pin Interrupt Enable Falling Edge / Active Level register */
54 __IO uint32_t CIENF; /*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */
55 __IO uint32_t RISE; /*!< Pin Interrupt Rising Edge register */
56 __IO uint32_t FALL; /*!< Pin Interrupt Falling Edge register */
57 __IO uint32_t IST; /*!< Pin Interrupt Status register */
A Dritimer_15xx.h48 __IO uint32_t COMPVAL; /*!< Compare register */
49 …__IO uint32_t MASK; /*!< Mask register. This register holds the 32-bit mask value. A 1 written t…
50 __IO uint32_t CTRL; /*!< Control register */
51 __IO uint32_t COUNTER; /*!< 32-bit counter */
52 __IO uint32_t COMPVAL_H; /*!< Compare upper register */
53 __IO uint32_t MASK_H; /*!< Mask upper register */
55 __IO uint32_t COUNTER_H; /*!< Counter upper register */
/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/Src/
A Dstm32f7xx_hal_nand.c303 __IO uint32_t data = 0; in HAL_NAND_Read_ID()
322 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; in HAL_NAND_Read_ID()
325 data = *(__IO uint32_t *)deviceAddress; in HAL_NAND_Read_ID()
367 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF; in HAL_NAND_Reset()
391 __IO uint32_t index = 0; in HAL_NAND_Read_Page()
468 __IO uint32_t index = 0; in HAL_NAND_Write_Page()
512 *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; in HAL_NAND_Write_Page()
558 __IO uint32_t index = 0; in HAL_NAND_Read_SpareArea()
634 __IO uint32_t index = 0; in HAL_NAND_Write_SpareArea()
677 *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; in HAL_NAND_Write_SpareArea()
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/external/platform/stm32f7xx/STM32F7xx_HAL_Driver/CMSIS/
A Dstm32f756xx.h433 __IO uint32_t MACCR;
434 __IO uint32_t MACFFR;
435 __IO uint32_t MACHTHR;
439 __IO uint32_t MACFCR;
446 __IO uint32_t MACIMR;
457 __IO uint32_t MMCRIR;
458 __IO uint32_t MMCTIR;
484 __IO uint32_t DMABMR;
489 __IO uint32_t DMASR;
490 __IO uint32_t DMAOMR;
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A Dstm32f746xx.h432 __IO uint32_t MACCR;
433 __IO uint32_t MACFFR;
434 __IO uint32_t MACHTHR;
438 __IO uint32_t MACFCR;
445 __IO uint32_t MACIMR;
456 __IO uint32_t MMCRIR;
457 __IO uint32_t MMCTIR;
483 __IO uint32_t DMABMR;
488 __IO uint32_t DMASR;
489 __IO uint32_t DMAOMR;
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A Dstm32f745xx.h430 __IO uint32_t MACCR;
431 __IO uint32_t MACFFR;
432 __IO uint32_t MACHTHR;
436 __IO uint32_t MACFCR;
443 __IO uint32_t MACIMR;
454 __IO uint32_t MMCRIR;
455 __IO uint32_t MMCTIR;
481 __IO uint32_t DMABMR;
486 __IO uint32_t DMASR;
487 __IO uint32_t DMAOMR;
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/external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/CMSIS/
A Dstm32f2xx.h499 __IO uint32_t MACCR;
500 __IO uint32_t MACFFR;
501 __IO uint32_t MACHTHR;
505 __IO uint32_t MACFCR;
512 __IO uint32_t MACIMR;
523 __IO uint32_t MMCRIR;
524 __IO uint32_t MMCTIR;
550 __IO uint32_t DMABMR;
555 __IO uint32_t DMASR;
556 __IO uint32_t DMAOMR;
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/external/platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/CMSIS/
A Dstm32f4xx.h1231 __IO uint32_t MACCR;
1232 __IO uint32_t MACFFR;
1233 __IO uint32_t MACHTHR;
1237 __IO uint32_t MACFCR;
1244 __IO uint32_t MACIMR;
1255 __IO uint32_t MMCRIR;
1256 __IO uint32_t MMCTIR;
1282 __IO uint32_t DMABMR;
1287 __IO uint32_t DMASR;
1288 __IO uint32_t DMAOMR;
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/external/platform/stm32f4xx/STM32F4xx_StdPeriph_Driver/src/
A Dstm32f4xx_flash.c758 *(__IO uint64_t*)Address = Data; in FLASH_ProgramDoubleWord()
801 *(__IO uint32_t*)Address = Data; in FLASH_ProgramWord()
843 *(__IO uint16_t*)Address = Data; in FLASH_ProgramHalfWord()
885 *(__IO uint8_t*)Address = Data; in FLASH_ProgramByte()
1212 *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; in FLASH_OB_RDPConfig()
1281 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT; in FLASH_OB_BootConfig()
1302 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; in FLASH_OB_BORConfig()
1345 return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); in FLASH_OB_GetWRP()
1359 return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); in FLASH_OB_GetWRP1()
1373 return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); in FLASH_OB_GetPCROP()
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A Dstm32f4xx_pwr.c181 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; in PWR_BackupAccessCmd()
254 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; in PWR_PVDCmd()
289 *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; in PWR_WakeUpPinCmd()
421 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState; in PWR_BackupRegulatorCmd()
479 *(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState; in PWR_OverDriveCmd()
497 *(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState; in PWR_OverDriveSWCmd()
552 *(__IO uint32_t *) CR_MRUDS_BB = (uint32_t)ENABLE; in PWR_MainRegulatorUnderDriveCmd()
556 *(__IO uint32_t *) CR_MRUDS_BB = (uint32_t)DISABLE; in PWR_MainRegulatorUnderDriveCmd()
576 *(__IO uint32_t *) CR_LPUDS_BB = (uint32_t)ENABLE; in PWR_LowRegulatorUnderDriveCmd()
580 *(__IO uint32_t *) CR_LPUDS_BB = (uint32_t)DISABLE; in PWR_LowRegulatorUnderDriveCmd()
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/external/platform/stm32f1xx/STM32F10x_StdPeriph_Driver/CMSIS/
A Dstm32f10x.h531 __IO uint32_t SR;
550 __IO uint32_t DR;
582 __IO uint16_t CR;
740 __IO uint32_t DR;
744 __IO uint32_t CR;
753 __IO uint32_t CR;
767 __IO uint32_t SR;
881 __IO uint32_t PR;
893 __IO uint32_t SR;
894 __IO uint32_t CR;
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/external/platform/stm32f1xx/STM32F10x_StdPeriph_Driver/src/
A Dstm32f10x_bkp.c137 *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; in BKP_TamperPinLevelConfig()
150 *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; in BKP_TamperPinCmd()
163 *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; in BKP_ITConfig()
223 __IO uint32_t tmp = 0; in BKP_WriteBackupRegister()
231 *(__IO uint32_t *) tmp = Data; in BKP_WriteBackupRegister()
242 __IO uint32_t tmp = 0; in BKP_ReadBackupRegister()
250 return (*(__IO uint16_t *) tmp); in BKP_ReadBackupRegister()
260 return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); in BKP_GetFlagStatus()
281 return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); in BKP_GetITStatus()
/external/platform/stm32f0xx/CMSIS/inc/
A Dstm32f070x6.h435 __IO uint16_t RESERVED0; /*!< Reserved */
437 __IO uint16_t RESERVED1; /*!< Reserved */
439 __IO uint16_t RESERVED2; /*!< Reserved */
441 __IO uint16_t RESERVED3; /*!< Reserved */
443 __IO uint16_t RESERVED4; /*!< Reserved */
445 __IO uint16_t RESERVED5; /*!< Reserved */
447 __IO uint16_t RESERVED6; /*!< Reserved */
449 __IO uint16_t RESERVED7[17]; /*!< Reserved */
451 __IO uint16_t RESERVED8; /*!< Reserved */
453 __IO uint16_t RESERVED9; /*!< Reserved */
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A Dstm32f070xb.h444 __IO uint16_t RESERVED0; /*!< Reserved */
446 __IO uint16_t RESERVED1; /*!< Reserved */
448 __IO uint16_t RESERVED2; /*!< Reserved */
450 __IO uint16_t RESERVED3; /*!< Reserved */
452 __IO uint16_t RESERVED4; /*!< Reserved */
454 __IO uint16_t RESERVED5; /*!< Reserved */
456 __IO uint16_t RESERVED6; /*!< Reserved */
458 __IO uint16_t RESERVED7[17]; /*!< Reserved */
460 __IO uint16_t RESERVED8; /*!< Reserved */
462 __IO uint16_t RESERVED9; /*!< Reserved */
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A Dstm32f058xx.h247 __IO uint32_t CCR; /*!< DMA channel x configuration register */
248 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
249 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
357 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
358 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
359 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
360 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
361 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
520 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
521 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
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A Dstm32f051x8.h248 __IO uint32_t CCR; /*!< DMA channel x configuration register */
249 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
250 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
358 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
359 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
360 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
361 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
362 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
521 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
522 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
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A Dstm32f030x8.h193 __IO uint32_t CCR; /*!< DMA channel x configuration register */
194 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
195 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
303 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
304 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
305 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
306 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
307 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
437 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
438 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
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A Dstm32f030x6.h188 __IO uint32_t CCR; /*!< DMA channel x configuration register */
189 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
190 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
297 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
298 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
299 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
300 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
301 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
431 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
432 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
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A Dstm32f071xb.h266 __IO uint32_t CCR; /*!< DMA channel x configuration register */
267 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
268 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
378 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
379 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
380 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
381 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
382 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
541 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
542 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
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/external/platform/stm32f2xx/STM32F2xx_StdPeriph_Driver/src/
A Dstm32f2xx_flash.c176 *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency; in FLASH_SetLatency()
480 *(__IO uint64_t*)Address = Data; in FLASH_ProgramDoubleWord()
518 *(__IO uint32_t*)Address = Data; in FLASH_ProgramWord()
556 *(__IO uint16_t*)Address = Data; in FLASH_ProgramHalfWord()
594 *(__IO uint8_t*)Address = Data; in FLASH_ProgramByte()
707 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP); in FLASH_OB_WRPConfig()
739 *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; in FLASH_OB_RDPConfig()
800 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; in FLASH_OB_BORConfig()
815 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; in FLASH_OB_Launch()
843 return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); in FLASH_OB_GetWRP()
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