| /external/platform/nrfx/mdk/ |
| A D | nrf5340_application.h | 146 #define __IOM __IO macro
164 …__IOM uint32_t DATA0; /*!< (@ 0x00000000) Description cluster: Cache data …
166 …__IOM uint32_t DATA1; /*!< (@ 0x00000004) Description cluster: Cache data …
168 …__IOM uint32_t DATA2; /*!< (@ 0x00000008) Description cluster: Cache data …
170 …__IOM uint32_t DATA3; /*!< (@ 0x0000000C) Description cluster: Cache data …
187 …__IOM uint32_t WAY[2]; /*!< (@ 0x00000000) Description collection: Cache in…
398 …__IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define whic…
507 …__IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPRO…
736 …__IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input confi…
767 …__IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe c…
[all …]
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| A D | nrf5340_network.h | 125 #define __IOM __IO macro
170 …__IOM uint32_t VREQH; /*!< (@ 0x00000000) Request high voltage on RADIO Af…
198 …__IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPRO…
211 …__IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the APPRO…
220 …__IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin sele…
248 …__IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe c…
250 …__IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe c…
293 …__IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of…
446 …__IOM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAM[n] powe…
779 …__IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred…
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| A D | nrf52.h | 151 #define __IOM __IO macro
454 …__IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[0]: Last res…
456 …__IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[0]: Last res…
501 …__IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[0]: Beginnin…
505 …__IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[0]: Amount o…
508 …__IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[0]: Time add…
518 …__IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[0]: Outpu…
536 …__IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write sam…
577 …__IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read acc…
626 …__IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[0]: Subregio…
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| A D | nrf52811.h | 141 #define __IOM __IO macro
237 …__IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin sele…
444 …__IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result…
446 …__IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result…
459 …__IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input confi…
491 …__IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning a…
495 …__IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of a…
507 …__IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output p…
525 …__IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write sam…
791 …__IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred…
[all …]
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| A D | nrf52840.h | 157 #define __IOM __IO macro
368 …__IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of…
508 …__IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result…
510 …__IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result…
523 …__IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input confi…
556 …__IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning a…
560 …__IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of a…
590 …__IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write sam…
645 …__IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access…
781 …__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum num…
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| A D | nrf9160.h | 148 #define __IOM __IO macro
208 …__IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination…
266 …__IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select betw…
277 …__IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select betw…
289 …__IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define whic…
301 …__IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define whic…
354 …__IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock register ERASEPROTECT.DISAB…
548 …__IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input confi…
579 …__IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe c…
581 …__IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe c…
[all …]
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| A D | nrf52833.h | 155 #define __IOM __IO macro
265 …__IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin sele…
370 …__IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of…
510 …__IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result…
512 …__IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result…
525 …__IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input confi…
558 …__IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning a…
592 …__IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write sam…
647 …__IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access…
783 …__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum num…
[all …]
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| A D | nrf52810.h | 141 #define __IOM __IO macro
425 …__IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result…
427 …__IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result…
440 …__IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input confi…
472 …__IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning a…
476 …__IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of a…
488 …__IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output p…
506 …__IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write sam…
601 …__IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping …
766 …__IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred…
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| A D | nrf52805.h | 138 #define __IOM __IO macro
422 …__IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result…
424 …__IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result…
437 …__IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input confi…
553 …__IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping …
718 …__IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred…
873 …__IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is re…
937 …__IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends …
969 …__IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TW…
975 …__IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to trans…
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| A D | nrf52820.h | 140 #define __IOM __IO macro
231 …__IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin sele…
448 …__IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start addre…
516 …__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum num…
539 …__IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum num…
622 …__IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping …
628 …__IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulat…
801 …__IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred…
810 …__IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection com…
1034 …__IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends …
[all …]
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| A D | nrf51.h | 133 #define __IOM __IO macro
236 …__IOM uint32_t RESET; /*!< (@ 0x00000544) Pin reset functionality configur…
308 …__IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable erase and write protecti…
343 …__IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred…
349 …__IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count va…
434 …__IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source. Write error field …
528 …__IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Two-wire error source. Write err…
722 …__IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable events routing to PPI. Th…
724 …__IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable events routing to PPI. T…
751 …__IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete…
[all …]
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| /external/arch/arm/arm-m/CMSIS/Include/ |
| A D | core_cm23.h | 614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
619 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
623 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
627 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
631 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
635 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
639 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
643 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
748 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
749 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
[all …]
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| A D | core_cm33.h | 1116 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1118 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1121 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1126 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1130 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1134 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1138 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1142 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1321 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1322 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
[all …]
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| A D | core_cm35p.h | 1116 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1118 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1121 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1126 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1130 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1134 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1138 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1142 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1321 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1322 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
[all …]
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| A D | core_sc300.h | 833 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
835 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
838 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
842 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
843 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
846 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
847 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
850 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
854 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
999 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
[all …]
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| A D | core_armv8mbl.h | 614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
619 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
623 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
627 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
631 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
635 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
639 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
643 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
647 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
651 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
[all …]
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| A D | core_armv8mml.h | 1116 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1118 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1121 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1126 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1130 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1134 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1138 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1142 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1146 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1150 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
[all …]
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| A D | core_cm3.h | 848 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
850 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
853 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
857 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
858 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
861 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
862 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
865 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
869 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
1014 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
[all …]
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| A D | core_cm4.h | 906 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
908 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
911 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
915 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
916 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
919 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
920 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
923 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
927 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
1072 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
[all …]
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| A D | core_cm7.h | 1130 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1132 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1135 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1139 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
1140 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1143 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
1144 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1147 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
1151 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
1299 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
[all …]
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| A D | core_cm55.h | 1178 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1180 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1183 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1188 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1192 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1196 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1200 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1204 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1364 __IOM uint32_t CPDLPSTATE;
1365 __IOM uint32_t DPDLPSTATE;
[all …]
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| A D | core_armv81mml.h | 1178 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1180 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1183 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1188 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1192 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1196 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1200 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1204 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1208 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1212 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
[all …]
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| A D | core_sc000.h | 180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
327 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
331 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
336 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
356 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
358 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
359 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
468 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
491 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
543 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
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| A D | core_cm0plus.h | 180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
332 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
334 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
360 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
475 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
[all …]
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| /external/platform/pico/rp2_common/cmsis/stub/CMSIS/Core/Include/ |
| A D | core_cm0plus.h | 180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro
330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
332 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
334 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
360 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
475 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
[all …]
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