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/external/platform/nrf51/include/platform/
A Dnrf518xx.h181__O uint32_t EN; /*!< Enable channel group. …
182__O uint32_t DIS; /*!< Disable channel group. …
202__O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. …
203__O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). …
214__O uint32_t SYSTEMOFF; /*!< System off register. …
821__O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operat…
824__O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto op…
850__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs spe…
886__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operat…
888__O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will …
[all …]
/external/platform/lpc15xx/lpcopen/lpc_chip_15xx/inc/
A Dcrc_15xx.h52 __O uint32_t WRDATA32; /*!< CRC Data Register: write size 32-bit*/
53 __O uint16_t WRDATA16; /*!< CRC Data Register: write size 16-bit*/
54 __O uint8_t WRDATA8; /*!< CRC Data Register: write size 8-bit*/
A Ddma_15xx.h50 __O uint32_t ENABLECLR; /*!< DMA Channel Enable Clear for all DMA channels */
60 __O uint32_t INTENCLR; /*!< DMA Interrupt Enable Clear for all DMA channels */
66 __O uint32_t SETVALID; /*!< DMA Set ValidPending control bits for all DMA channels */
68 __O uint32_t SETTRIG; /*!< DMA Set Trigger control bits for all DMA channels */
70 __O uint32_t ABORT; /*!< DMA Channel Abort control for all DMA channels */
A Dmrt_15xx.h55 __O uint32_t TIMER; /*!< Timer register */
66 __O uint32_t IDLE_CH;
A Dgpio_15xx.h55 __O uint32_t CLR[32]; /*!< Offset 0x2280: Clear port n */
56 __O uint32_t NOT[32]; /*!< Offset 0x2300: Toggle port n */
A Dwwdt_15xx.h50__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this …
A Di2c_common_15xx.h51__O uint32_t INTENCLR; /*!< I2C Interrupt Enable Clear Register common for Master, Slave and Moni…
A Duart_15xx.h54 __O uint32_t INTENCLR; /*!< Interrupt Enable clear register */
A Dspi_15xx.h51 __O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. register*/
/external/platform/pico/rp2_common/cmsis/stub/CMSIS/Device/RaspberryPi/RP2040/Include/
A DRP2040.h99 #define __OM __O
/external/arch/arm/arm-m/CMSIS/Include/
A Dcore_cm0.h164 #define __O volatile /*!< Defines 'write only' permissions */ macro
A Dcore_cm1.h164 #define __O volatile /*!< Defines 'write only' permissions */ macro
A Dcore_sc000.h174 #define __O volatile /*!< Defines 'write only' permissions */ macro
A Dcore_cm0plus.h174 #define __O volatile /*!< Defines 'write only' permissions */ macro
A Dcore_cm3.h174 #define __O volatile /*!< Defines 'write only' permissions */ macro
A Dcore_sc300.h174 #define __O volatile /*!< Defines 'write only' permissions */ macro
A Dcore_cm4.h226 #define __O volatile /*!< Defines 'write only' permissions */ macro
A Dcore_armv8mbl.h197 #define __O volatile /*!< Defines 'write only' permissions */ macro
A Dcore_cm23.h197 #define __O volatile /*!< Defines 'write only' permissions */ macro
A Dcore_cm7.h241 #define __O volatile /*!< Defines 'write only' permissions */ macro
A Dcore_cm33.h282 #define __O volatile /*!< Defines 'write only' permissions */ macro
A Dcore_cm35p.h282 #define __O volatile /*!< Defines 'write only' permissions */ macro
/external/platform/pico/rp2_common/cmsis/stub/CMSIS/Core/Include/
A Dcore_cm0plus.h174 #define __O volatile /*!< Defines 'write only' permissions */ macro
/external/platform/nrfx/mdk/
A Dnrf51.h130 #define __OM __O
A Dnrf52805.h135 #define __OM __O

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