Searched refs:_u (Results 1 – 25 of 34) sorted by relevance
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1013 #define CLOCKS_FC0_REF_KHZ_MSB _u(19)1014 #define CLOCKS_FC0_REF_KHZ_LSB _u(0)1023 #define CLOCKS_FC0_MIN_KHZ_MSB _u(24)1024 #define CLOCKS_FC0_MIN_KHZ_LSB _u(0)1033 #define CLOCKS_FC0_MAX_KHZ_MSB _u(24)1034 #define CLOCKS_FC0_MAX_KHZ_LSB _u(0)1044 #define CLOCKS_FC0_DELAY_MSB _u(2)1045 #define CLOCKS_FC0_DELAY_LSB _u(0)1055 #define CLOCKS_FC0_INTERVAL_MSB _u(3)1056 #define CLOCKS_FC0_INTERVAL_LSB _u(0)[all …]
17 #define USB_ADDR_ENDP_OFFSET _u(0x00000000)18 #define USB_ADDR_ENDP_BITS _u(0x000f007f)19 #define USB_ADDR_ENDP_RESET _u(0x00000000)23 #define USB_ADDR_ENDP_ENDPOINT_RESET _u(0x0)25 #define USB_ADDR_ENDP_ENDPOINT_MSB _u(19)26 #define USB_ADDR_ENDP_ENDPOINT_LSB _u(16)35 #define USB_ADDR_ENDP_ADDRESS_MSB _u(6)36 #define USB_ADDR_ENDP_ADDRESS_LSB _u(0)667 #define USB_SOF_WR_COUNT_LSB _u(0)683 #define USB_SOF_RD_COUNT_LSB _u(0)[all …]
17 #define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000)18 #define IO_BANK0_GPIO0_STATUS_BITS _u(0x050a3300)19 #define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000)23 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0)25 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26)26 #define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26)57 #define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _u(13)58 #define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _u(13)89 #define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004)90 #define IO_BANK0_GPIO0_CTRL_BITS _u(0x3003331f)[all …]
17 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_OFFSET _u(0x00000000)18 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BITS _u(0xffffffff)19 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET _u(0x00000000)25 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB _u(31)26 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_LSB _u(16)34 #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_LSB _u(8)69 #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_OFFSET _u(0x00000008)70 #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BITS _u(0xfc03ffff)71 #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_RESET _u(0x00000000)78 #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_MSB _u(31)[all …]
23 #define DMA_CH0_READ_ADDR_MSB _u(31)24 #define DMA_CH0_READ_ADDR_LSB _u(0)4691 #define DMA_INTR_MSB _u(15)4692 #define DMA_INTR_LSB _u(0)4701 #define DMA_INTE0_MSB _u(15)4702 #define DMA_INTE0_LSB _u(0)4713 #define DMA_INTF0_LSB _u(0)4725 #define DMA_INTS0_LSB _u(0)4735 #define DMA_INTE1_LSB _u(0)4746 #define DMA_INTF1_LSB _u(0)[all …]
37 #define PADS_BANK0_GPIO0_OD_RESET _u(0x0)39 #define PADS_BANK0_GPIO0_OD_MSB _u(7)40 #define PADS_BANK0_GPIO0_OD_LSB _u(7)45 #define PADS_BANK0_GPIO0_IE_RESET _u(0x1)47 #define PADS_BANK0_GPIO0_IE_MSB _u(6)48 #define PADS_BANK0_GPIO0_IE_LSB _u(6)71 #define PADS_BANK0_GPIO0_PUE_MSB _u(3)72 #define PADS_BANK0_GPIO0_PUE_LSB _u(3)110 #define PADS_BANK0_GPIO1_OD_MSB _u(7)111 #define PADS_BANK0_GPIO1_OD_LSB _u(7)[all …]
953 #define IO_QSPI_INTR_OFFSET _u(0x00000030)954 #define IO_QSPI_INTR_BITS _u(0x00ffffff)955 #define IO_QSPI_INTR_RESET _u(0x00000000)1151 #define IO_QSPI_PROC0_INTE_OFFSET _u(0x00000034)1152 #define IO_QSPI_PROC0_INTE_BITS _u(0x00ffffff)1153 #define IO_QSPI_PROC0_INTE_RESET _u(0x00000000)1349 #define IO_QSPI_PROC0_INTF_OFFSET _u(0x00000038)1350 #define IO_QSPI_PROC0_INTF_BITS _u(0x00ffffff)1351 #define IO_QSPI_PROC0_INTF_RESET _u(0x00000000)1547 #define IO_QSPI_PROC0_INTS_OFFSET _u(0x0000003c)[all …]
243 #define PIO_TXF0_MSB _u(31)244 #define PIO_TXF0_LSB _u(0)256 #define PIO_TXF1_LSB _u(0)268 #define PIO_TXF2_LSB _u(0)280 #define PIO_TXF3_LSB _u(0)293 #define PIO_RXF0_LSB _u(0)306 #define PIO_RXF1_LSB _u(0)319 #define PIO_RXF2_LSB _u(0)332 #define PIO_RXF3_LSB _u(0)349 #define PIO_IRQ_MSB _u(7)[all …]
98 #define I2C_IC_CON_OFFSET _u(0x00000000)99 #define I2C_IC_CON_BITS _u(0x000007ff)100 #define I2C_IC_CON_RESET _u(0x00000065)300 #define I2C_IC_TAR_OFFSET _u(0x00000004)301 #define I2C_IC_TAR_BITS _u(0x00000fff)302 #define I2C_IC_TAR_RESET _u(0x00000055)354 #define I2C_IC_TAR_IC_TAR_MSB _u(9)355 #define I2C_IC_TAR_IC_TAR_LSB _u(0)360 #define I2C_IC_SAR_OFFSET _u(0x00000008)380 #define I2C_IC_SAR_IC_SAR_MSB _u(9)[all …]
24 #define SIO_CPUID_MSB _u(31)25 #define SIO_CPUID_LSB _u(0)34 #define SIO_GPIO_IN_MSB _u(29)35 #define SIO_GPIO_IN_LSB _u(0)45 #define SIO_GPIO_HI_IN_MSB _u(5)46 #define SIO_GPIO_HI_IN_LSB _u(0)62 #define SIO_GPIO_OUT_MSB _u(29)63 #define SIO_GPIO_OUT_LSB _u(0)110 #define SIO_GPIO_OE_MSB _u(29)111 #define SIO_GPIO_OE_LSB _u(0)[all …]
122 #define PWM_CH0_CTR_MSB _u(15)123 #define PWM_CH0_CTR_LSB _u(0)136 #define PWM_CH0_CC_B_MSB _u(31)137 #define PWM_CH0_CC_B_LSB _u(16)145 #define PWM_CH0_CC_A_LSB _u(0)153 #define PWM_CH0_TOP_MSB _u(15)154 #define PWM_CH0_TOP_LSB _u(0)265 #define PWM_CH1_CTR_LSB _u(0)296 #define PWM_CH1_TOP_LSB _u(0)407 #define PWM_CH2_CTR_LSB _u(0)[all …]
18 #define M0PLUS_SYST_CSR_OFFSET _u(0x0000e010)19 #define M0PLUS_SYST_CSR_BITS _u(0x00010007)20 #define M0PLUS_SYST_CSR_RESET _u(0x00000000)51 #define M0PLUS_SYST_CSR_TICKINT_MSB _u(1)52 #define M0PLUS_SYST_CSR_TICKINT_LSB _u(1)61 #define M0PLUS_SYST_CSR_ENABLE_MSB _u(0)62 #define M0PLUS_SYST_CSR_ENABLE_LSB _u(0)86 #define M0PLUS_SYST_RVR_RELOAD_LSB _u(0)600 #define M0PLUS_CPUID_PARTNO_LSB _u(4)750 #define M0PLUS_VTOR_TBLOFF_MSB _u(31)[all …]
17 #define UART_UARTDR_OFFSET _u(0x00000000)28 #define UART_UARTDR_OE_MSB _u(11)29 #define UART_UARTDR_OE_LSB _u(11)44 #define UART_UARTDR_BE_MSB _u(10)45 #define UART_UARTDR_BE_LSB _u(10)56 #define UART_UARTDR_PE_MSB _u(9)57 #define UART_UARTDR_PE_LSB _u(9)67 #define UART_UARTDR_FE_MSB _u(8)68 #define UART_UARTDR_FE_LSB _u(8)151 #define UART_UARTFR_RI_MSB _u(8)[all …]
253 #define SSI_SER_MSB _u(0)254 #define SSI_SER_LSB _u(0)345 #define SSI_SR_TXE_MSB _u(5)346 #define SSI_SR_TXE_LSB _u(5)353 #define SSI_SR_RFF_MSB _u(4)354 #define SSI_SR_RFF_LSB _u(4)369 #define SSI_SR_TFE_MSB _u(2)370 #define SSI_SR_TFE_LSB _u(2)557 #define SSI_TXOICR_MSB _u(0)597 #define SSI_ICR_MSB _u(0)[all …]
18 #define RESETS_RESET_OFFSET _u(0x00000000)19 #define RESETS_RESET_BITS _u(0x01ffffff)20 #define RESETS_RESET_RESET _u(0x01ffffff)34 #define RESETS_RESET_UART1_MSB _u(23)35 #define RESETS_RESET_UART1_LSB _u(23)42 #define RESETS_RESET_UART0_MSB _u(22)43 #define RESETS_RESET_UART0_LSB _u(22)98 #define RESETS_RESET_RTC_MSB _u(15)99 #define RESETS_RESET_RTC_LSB _u(15)106 #define RESETS_RESET_PWM_MSB _u(14)[all …]
17 #define PSM_FRCE_ON_OFFSET _u(0x00000000)23 #define PSM_FRCE_ON_PROC1_RESET _u(0x0)25 #define PSM_FRCE_ON_PROC1_MSB _u(16)26 #define PSM_FRCE_ON_PROC1_LSB _u(16)39 #define PSM_FRCE_ON_SIO_RESET _u(0x0)41 #define PSM_FRCE_ON_SIO_MSB _u(14)42 #define PSM_FRCE_ON_SIO_LSB _u(14)57 #define PSM_FRCE_ON_XIP_MSB _u(12)58 #define PSM_FRCE_ON_XIP_LSB _u(12)540 #define PSM_DONE_ROM_MSB _u(5)[all …]
29 #define SPI_SSPCR0_SCR_MSB _u(15)30 #define SPI_SSPCR0_SCR_LSB _u(8)38 #define SPI_SSPCR0_SPH_MSB _u(7)39 #define SPI_SSPCR0_SPH_LSB _u(7)47 #define SPI_SSPCR0_SPO_MSB _u(6)48 #define SPI_SSPCR0_SPO_LSB _u(6)57 #define SPI_SSPCR0_FRF_MSB _u(5)58 #define SPI_SSPCR0_FRF_LSB _u(4)70 #define SPI_SSPCR0_DSS_MSB _u(3)103 #define SPI_SSPCR1_MS_MSB _u(2)[all …]
22 #define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0)23 #define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0)25 #define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)26 #define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)39 #define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7)40 #define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7)47 #define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6)48 #define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6)110 #define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7)111 #define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7)[all …]
21 #define RTC_CLKDIV_M1_MSB _u(15)22 #define RTC_CLKDIV_M1_LSB _u(0)51 #define RTC_SETUP_0_DAY_MSB _u(4)52 #define RTC_SETUP_0_DAY_LSB _u(0)112 #define RTC_CTRL_LOAD_MSB _u(4)113 #define RTC_CTRL_LOAD_LSB _u(4)352 #define RTC_INTR_RTC_MSB _u(0)353 #define RTC_INTR_RTC_LSB _u(0)366 #define RTC_INTE_RTC_MSB _u(0)367 #define RTC_INTE_RTC_LSB _u(0)[all …]
34 #define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8)64 #define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0)65 #define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0)77 #define BUSCTRL_PERFCTR0_MSB _u(23)78 #define BUSCTRL_PERFCTR0_LSB _u(0)141 #define BUSCTRL_PERFCTR1_MSB _u(23)142 #define BUSCTRL_PERFCTR1_LSB _u(0)205 #define BUSCTRL_PERFCTR2_MSB _u(23)206 #define BUSCTRL_PERFCTR2_LSB _u(0)269 #define BUSCTRL_PERFCTR3_MSB _u(23)[all …]
37 #define TIMER_TIMEHW_MSB _u(31)38 #define TIMER_TIMEHW_LSB _u(0)47 #define TIMER_TIMELW_MSB _u(31)48 #define TIMER_TIMELW_LSB _u(0)57 #define TIMER_TIMEHR_MSB _u(31)58 #define TIMER_TIMEHR_LSB _u(0)67 #define TIMER_TIMELR_LSB _u(0)79 #define TIMER_ALARM0_LSB _u(0)91 #define TIMER_ALARM1_LSB _u(0)126 #define TIMER_ARMED_MSB _u(3)[all …]
17 #define ADC_CS_OFFSET _u(0x00000000)18 #define ADC_CS_BITS _u(0x001f770f)19 #define ADC_CS_RESET _u(0x00000000)57 #define ADC_CS_ERR_RESET _u(0x0)59 #define ADC_CS_ERR_MSB _u(9)60 #define ADC_CS_ERR_LSB _u(9)69 #define ADC_CS_READY_MSB _u(8)102 #define ADC_CS_EN_RESET _u(0x0)104 #define ADC_CS_EN_MSB _u(0)105 #define ADC_CS_EN_LSB _u(0)[all …]
17 #define ROSC_CTRL_OFFSET _u(0x00000000)18 #define ROSC_CTRL_BITS _u(0x00ffffff)19 #define ROSC_CTRL_RESET _u(0x00000aa0)103 #define ROSC_FREQA_DS2_LSB _u(8)110 #define ROSC_FREQA_DS1_MSB _u(6)111 #define ROSC_FREQA_DS1_LSB _u(4)118 #define ROSC_FREQA_DS0_MSB _u(2)199 #define ROSC_DIV_MSB _u(11)200 #define ROSC_DIV_LSB _u(0)308 #define ROSC_COUNT_MSB _u(7)[all …]
21 #define SYSCFG_PROC0_NMI_MASK_MSB _u(31)22 #define SYSCFG_PROC0_NMI_MASK_LSB _u(0)31 #define SYSCFG_PROC1_NMI_MASK_MSB _u(31)32 #define SYSCFG_PROC1_NMI_MASK_LSB _u(0)37 #define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000008)38 #define SYSCFG_PROC_CONFIG_BITS _u(0xff000003)115 #define SYSCFG_DBGFORCE_OFFSET _u(0x00000014)116 #define SYSCFG_DBGFORCE_BITS _u(0x000000ff)117 #define SYSCFG_DBGFORCE_RESET _u(0x00000066)197 #define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7)[all …]
20 #define WATCHDOG_CTRL_OFFSET _u(0x00000000)21 #define WATCHDOG_CTRL_BITS _u(0xc7ffffff)22 #define WATCHDOG_CTRL_RESET _u(0x07000000)70 #define WATCHDOG_CTRL_TIME_LSB _u(0)80 #define WATCHDOG_LOAD_MSB _u(23)81 #define WATCHDOG_LOAD_LSB _u(0)114 #define WATCHDOG_SCRATCH0_LSB _u(0)124 #define WATCHDOG_SCRATCH1_LSB _u(0)134 #define WATCHDOG_SCRATCH2_LSB _u(0)144 #define WATCHDOG_SCRATCH3_LSB _u(0)[all …]
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