Home
last modified time | relevance | path

Searched refs:at (Results 1 – 25 of 45) sorted by relevance

12

/external/platform/nrfx/mdk/
A Darm_startup_nrf52810.s7 ; You may obtain a copy of the License at
62 ; Vector Table Mapped to Address 0 at Reset
214 ; Workaround for Errata 185 RAM: RAM corruption at extreme corners
215 ; found at the Errata document for your device located
216 ; at https://infocenter.nordicsemi.com/index.jsp
A Diar_startup_nrf51.s7 ; You may obtain a copy of the License at
25 ; The vector table is normally located at address 0.
26 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
A Diar_startup_nrf52805.s7 ; You may obtain a copy of the License at
25 ; The vector table is normally located at address 0.
26 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
A Diar_startup_nrf5340_network.s7 ; You may obtain a copy of the License at
25 ; The vector table is normally located at address 0.
26 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
A Diar_startup_nrf52811.s7 ; You may obtain a copy of the License at
25 ; The vector table is normally located at address 0.
26 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
A Diar_startup_nrf52820.s7 ; You may obtain a copy of the License at
25 ; The vector table is normally located at address 0.
26 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
A Darm_startup_nrf51.s7 ; You may obtain a copy of the License at
62 ; Vector Table Mapped to Address 0 at Reset
A Diar_startup_nrf52.s7 ; You may obtain a copy of the License at
25 ; The vector table is normally located at address 0.
26 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
A Diar_startup_nrf52810.s7 ; You may obtain a copy of the License at
25 ; The vector table is normally located at address 0.
26 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
A Diar_startup_nrf52833.s7 ; You may obtain a copy of the License at
25 ; The vector table is normally located at address 0.
26 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
A Diar_startup_nrf52840.s7 ; You may obtain a copy of the License at
25 ; The vector table is normally located at address 0.
26 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
A Darm_startup_nrf52805.s7 ; You may obtain a copy of the License at
62 ; Vector Table Mapped to Address 0 at Reset
A Darm_startup_nrf52811.s7 ; You may obtain a copy of the License at
62 ; Vector Table Mapped to Address 0 at Reset
A Darm_startup_nrf52820.s7 ; You may obtain a copy of the License at
62 ; Vector Table Mapped to Address 0 at Reset
A Darm_startup_nrf5340_network.s7 ; You may obtain a copy of the License at
62 ; Vector Table Mapped to Address 0 at Reset
A Diar_startup_nrf5340_application.s7 ; You may obtain a copy of the License at
25 ; The vector table is normally located at address 0.
26 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
A Diar_startup_nrf9160.s7 ; You may obtain a copy of the License at
25 ; The vector table is normally located at address 0.
26 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
/external/platform/lpc15xx/lpcopen/periph_dac/example/
A Dreadme.dox37 * This example uses the DAC to produce a stepped saw tooth waveform at 100Hz.
39 * The timer is set up to generate interrupts at 2KHz i.e. 20 DAC output samples
44 * waveform at 100Hz.<br>
/external/platform/pico/rp2_common/pico_async_context/include/pico/
A Dasync_context.h294 …d_at_time_worker_at(async_context_t *context, async_at_time_worker_t *worker, absolute_time_t at) { in async_context_add_at_time_worker_at() argument
295 worker->next_time = at; in async_context_add_at_time_worker_at()
/external/platform/lpc15xx/lpcopen/periph_gpio/example/
A Dreadme.dox36 * for multiple GPIO pin functions at once. The example will operate on multiple GPIO
37 * pins at once usnig the GPIO direction setup and masked write oeprations.<br>
/external/platform/pico/rp2_common/pico_standard_link/
A Dmemmap_no_flash.ld38 binaries directly at their lowest address (preferring main RAM over XIP
191 /* by default we put core 0 stack at the end of scratch Y, so that if core 1
A Dmemmap_copy_to_ram.ld54 /* The second stage will always enter the image at the start of .text.
223 /* by default we put core 0 stack at the end of scratch Y, so that if core 1
A Dmemmap_blocked_ram.ld54 /* The second stage will always enter the image at the start of .text.
221 /* by default we put core 0 stack at the end of scratch Y, so that if core 1
A Dmemmap_default.ld54 /* The second stage will always enter the image at the start of .text.
221 /* by default we put core 0 stack at the end of scratch Y, so that if core 1
/external/platform/pico/rp2_common/pico_mem_ops/
A Dmem_ops_aeabi.S28 # NOTE: All code sections are placed in RAM (at the expense of some veneer cost for calls from flas…

Completed in 37 milliseconds

12