1 /* 2 * @brief LPC15xx DMA ROM API declarations and functions 3 * 4 * @note 5 * Copyright(C) NXP Semiconductors, 2013 6 * All rights reserved. 7 * 8 * @par 9 * Software that is described herein is for illustrative purposes only 10 * which provides customers with programming information regarding the 11 * LPC products. This software is supplied "AS IS" without any warranties of 12 * any kind, and NXP Semiconductors and its licensor disclaim any and 13 * all warranties, express or implied, including all implied warranties of 14 * merchantability, fitness for a particular purpose and non-infringement of 15 * intellectual property rights. NXP Semiconductors assumes no responsibility 16 * or liability for the use of the software, conveys no license or rights under any 17 * patent, copyright, mask work right, or any other intellectual property rights in 18 * or to any products. NXP Semiconductors reserves the right to make changes 19 * in the software without notification. NXP Semiconductors also makes no 20 * representation or warranty that such application will be suitable for the 21 * specified use without further testing or modification. 22 * 23 * @par 24 * Permission to use, copy, modify, and distribute this software and its 25 * documentation is hereby granted, under NXP Semiconductors' and its 26 * licensor's relevant copyrights in the software, without fee, provided that it 27 * is used in conjunction with NXP Semiconductors microcontrollers. This 28 * copyright, permission, and disclaimer notice must appear in all copies of 29 * this code. 30 */ 31 32 #ifndef __ROM_DMA_15XX_H_ 33 #define __ROM_DMA_15XX_H_ 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 /** @defgroup DMAROM_15XX CHIP: LPC15xx DMA ROM API declarations and functions 40 * @ingroup ROMAPI_15XX 41 * @{ 42 */ 43 44 /* Bit definitions for DMA ROM Channel Configuration Structure */ 45 #define DMA_ROM_CH_EVENT_SWTRIG ((uint8_t) 0) 46 #define DMA_ROM_CH_EVENT_PERIPH ((uint8_t) 1) 47 #define DMA_ROM_CH_EVENT_HWTRIG ((uint8_t) 2) 48 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_1 ((uint8_t) 0 << 0) 49 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_2 ((uint8_t) 1 << 0) 50 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_4 ((uint8_t) 2 << 0) 51 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_8 ((uint8_t) 3 << 0) 52 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_16 ((uint8_t) 4 << 0) 53 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_32 ((uint8_t) 5 << 0) 54 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_64 ((uint8_t) 6 << 0) 55 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_128 ((uint8_t) 7 << 0) 56 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_256 ((uint8_t) 8 << 0) 57 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_512 ((uint8_t) 9 << 0) 58 #define DMA_ROM_CH_HWTRIG_BURSTPOWER_1024 ((uint8_t) 10 << 0) 59 #define DMA_ROM_CH_HWTRIG_SRC_WRAP_EN ((uint8_t) 1 << 4) 60 #define DMA_ROM_CH_HWTRIG_DEST_WRAP_EN ((uint8_t) 1 << 5) 61 #define DMA_ROM_CH_HWTRIG_BURST_EN ((uint8_t) 1 << 6) 62 /* Bit definitions for DMA ROM Task Configuration Structure */ 63 #define DMA_ROM_TASK_CFG_PING_PONG_EN ((uint8_t) 1 << 0) 64 #define DMA_ROM_TASK_CFG_SW_TRIGGER ((uint8_t) 1 << 1) 65 #define DMA_ROM_TASK_CFG_CLR_TRIGGER ((uint8_t) 1 << 2) 66 #define DMA_ROM_TASK_CFG_SEL_INTA ((uint8_t) 1 << 3) 67 #define DMA_ROM_TASK_CFG_SEL_INTB ((uint8_t) 1 << 4) 68 #define DMA_ROM_TASK_DATA_WIDTH_8 ((uint8_t) 0 ) 69 #define DMA_ROM_TASK_DATA_WIDTH_16 ((uint8_t) 1 ) 70 #define DMA_ROM_TASK_DATA_WIDTH_32 ((uint8_t) 2 ) 71 #define DMA_ROM_TASK_SRC_INC_0 ((uint8_t) 0 << 2) 72 #define DMA_ROM_TASK_SRC_INC_1 ((uint8_t) 1 << 2) 73 #define DMA_ROM_TASK_SRC_INC_2 ((uint8_t) 2 << 2) 74 #define DMA_ROM_TASK_SRC_INC_4 ((uint8_t) 3 << 2) 75 #define DMA_ROM_TASK_DEST_INC_0 ((uint8_t) 0 << 4) 76 #define DMA_ROM_TASK_DEST_INC_1 ((uint8_t) 1 << 4) 77 #define DMA_ROM_TASK_DEST_INC_2 ((uint8_t) 2 << 4) 78 #define DMA_ROM_TASK_DEST_INC_4 ((uint8_t) 3 << 4) 79 /** 80 * @brief DMA handle type 81 */ 82 typedef void *DMA_HANDLE_T; 83 84 /** 85 * @brief DMA channel callback function type 86 * @param res0: error code 87 * @param res1: 0 = INTA is issued, 1 = INTB is issued 88 */ 89 typedef void (*CALLBK_T)(uint32_t res0, uint32_t res1); 90 91 /** 92 * @brief DMA ROM drivers channel control structure 93 */ 94 typedef struct { 95 uint8_t event; /*!< event type selection for DMA transfer 96 - 0: software request 97 - 1: peripheral request 98 - 2: hardware trigger 99 - others: reserved */ 100 uint8_t hd_trigger; /*!< In case hardware trigger is enabled, the trigger burst is setup here. 101 NOTE: Rising edge triggered is fixed 102 - bit0~bit3: burst size 103 - 0: burst size =1, 1: 2^1, 2: 2^2,... 10: 1024, others: reserved. 104 - bit4: Source Burst Wrap 105 - 0: Source burst wrapping is not enabled 106 - 1: Source burst wrapping is enabled 107 - bit5: Destination Burst Wrap 108 - 0: Destination burst wrapping is not enabled 109 - 1: Destination burst wrapping is enabled 110 - bit6: Trigger Burst 111 - 0: Hardware trigger cause a single transfer 112 - 1: Hardware trigger cause a burst transfer 113 - bit7: reserved */ 114 uint8_t priority; /*!< priority level 115 - 0 -> 7: Highest priority -> Lowest priority. 116 - other: reserved. */ 117 uint8_t reserved0; 118 CALLBK_T cb_func; /*!< callback function, Callback function is 119 only invoked when INTA or INTB is enabled. */ 120 } DMA_CHANNEL_T; 121 122 /** 123 * @brief DMA ROM driver's TASK parameter structure 124 */ 125 typedef struct { 126 uint8_t ch_num; /*!< DMA channel number */ 127 uint8_t config; /*!< configuration of this task 128 - bit0: Ping_Pong transfer 129 - 0: Not Ping_Pong transfer 130 - 1: Linked with previous task for Ping_Pong transfer 131 - bit1: Software Trigger. 132 - 0: the trigger for this channel is not set. 133 - 1: the trigger for this channel is set immediately. 134 - bit2: Clear Trigger 135 - 0: The trigger is not cleared when this task is finished. 136 - 1: The trigger is cleared when this task is finished. 137 - bit3: Select INTA 138 - 0: No IntA. 139 - 1: The IntB flag for this channel will be set when this task is finished. 140 bit4: Select INTB 141 0: No IntB. 142 1: The IntB flag for this channel will be set when this task is finished. 143 bit5~bit7: reserved 144 */ 145 146 uint8_t data_type; /*!< 147 - bit0~bit1: Data width. 0: 8-bit, 1: 16-bit, 2: 32-bit, 3: reserved 148 - bit2~bit3: How is source address incremented? 149 - 0: The source address is not incremented for each transfer. 150 1: The source address is incremented by the amount specified by Width for each transfer. 151 2: The source address is incremented by 2 times the amount specified by Width for each transfer. 152 3: The source address is incremented by 4 times the amount specified by Width for each transfer. 153 - bit4~bit5: How is the destination address incremented? 154 0: The destination address is not incremented for each transfer. 155 1: The destination address is incremented by the amount specified by Width for each transfer. 156 2: The destination address is incremented by 2 times the amount specified by Width for each transfer. 157 3: The destination address is incremented by 4 times the amount specified by Width for each transfer. 158 - bit6~bit7: reserved. */ 159 uint8_t reserved0; 160 uint16_t data_length; /*!< 0: 1 transfer, 1: 2 transfer, ..., 1023: 1024 transfer. Others: reserved.*/ 161 uint16_t reserved1; 162 uint32_t src; /*!< Source data end address */ 163 uint32_t dst; /*!< Destination end address */ 164 uint32_t task_addr; /*!< the address of RAM for saving this task. 165 (NOTE: each task need 16 bytes RAM for storing configuration, 166 and DMA API could set it according user input parameter, 167 but it is responsible of user to allocate this RAM space and 168 make sure that the base address must be 16-byte alignment. 169 And if user has setup the next_task(!=0), the dma_task_link 170 must be called for this task setup, otherwise unpredictable error will happen.) */ 171 } DMA_TASK_T; 172 173 /** 174 * @brief DMA ROM API structure 175 * The DMA API handles DMA set-up and transfers. 176 */ 177 typedef struct DMAD_API { 178 /** DMA ISR routine */ 179 void (*dma_isr)(DMA_HANDLE_T *handle); 180 /** Get memory size needed for DMA. */ 181 uint32_t (*dma_get_mem_size)(void); 182 /** Set up DMA. */ 183 DMA_HANDLE_T * (*dma_setup)(uint32_t base_addr, uint8_t * ram); 184 /** Enable DMA channel and set-up basic DMA transfer. */ 185 ErrorCode_t (*dma_init)(DMA_HANDLE_T *handle, DMA_CHANNEL_T *channel, DMA_TASK_T *task); 186 /** Create linked transfer. */ 187 ErrorCode_t (*dma_link)(DMA_HANDLE_T *handle, DMA_TASK_T *task, uint8_t valid); 188 /** Set a task to valid. */ 189 ErrorCode_t (*dma_set_valid)(DMA_HANDLE_T *handle, uint8_t chl_num); 190 /** Pause DMA transfer on a given channel. */ 191 ErrorCode_t (*dma_pause)(DMA_HANDLE_T *handle, uint8_t chl_num); 192 /** Resume DMA transfer. */ 193 ErrorCode_t (*dma_unpause)(DMA_HANDLE_T *handle, uint8_t chl_num); 194 /** Cancel DMA transfer on a given channel.*/ 195 ErrorCode_t (*dma_abort)(DMA_HANDLE_T *handle, uint8_t chl_num); 196 } DMAD_API_T; 197 198 /** 199 * @} 200 */ 201 202 #ifdef __cplusplus 203 } 204 #endif 205 206 #endif /* __ROM_DMA_15XX_H_ */ 207