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Searched refs:hw_set_bits (Results 1 – 16 of 16) sorted by relevance

/external/platform/pico/rp2_common/hardware_rtc/
A Drtc.c111 hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS); in rtc_enable_alarm()
160 if (t->year >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_YEAR_ENA_BITS); in rtc_set_alarm()
161 if (t->month >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MONTH_ENA_BITS); in rtc_set_alarm()
162 if (t->day >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_DAY_ENA_BITS); in rtc_set_alarm()
163 if (t->dotw >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_DOTW_ENA_BITS); in rtc_set_alarm()
164 if (t->hour >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_HOUR_ENA_BITS); in rtc_set_alarm()
165 if (t->min >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_MIN_ENA_BITS); in rtc_set_alarm()
166 if (t->sec >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_SEC_ENA_BITS); in rtc_set_alarm()
/external/platform/pico/rp2_common/hardware_watchdog/
A Dwatchdog.c40 hw_set_bits(&psm_hw->wdsel, PSM_WDSEL_BITS & ~(PSM_WDSEL_ROSC_BITS | PSM_WDSEL_XOSC_BITS)); in _watchdog_enable()
47 hw_set_bits(&watchdog_hw->ctrl, dbg_bits); in _watchdog_enable()
53 hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_TRIGGER_BITS); in _watchdog_enable()
63 hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in _watchdog_enable()
/external/platform/pico/rp2_common/hardware_dma/include/hardware/
A Ddma.h545 hw_set_bits(&dma_hw->inte0, 1u << channel); in dma_channel_set_irq0_enabled()
558 hw_set_bits(&dma_hw->inte0, channel_mask); in dma_set_irq0_channel_mask_enabled()
574 hw_set_bits(&dma_hw->inte1, 1u << channel); in dma_channel_set_irq1_enabled()
587 hw_set_bits(&dma_hw->inte1, channel_mask); in dma_set_irq1_channel_mask_enabled()
741 hw_set_bits(&dma_hw->ch[channel].al1_ctrl, DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS); in dma_sniffer_enable()
765 hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS); in dma_sniffer_set_byte_swap_enabled()
780 hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_INV_BITS); in dma_sniffer_set_output_invert_enabled()
795 hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_REV_BITS); in dma_sniffer_set_output_reverse_enabled()
/external/platform/pico/rp2_common/hardware_adc/include/hardware/
A Dadc.h121 hw_set_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS); in adc_set_temp_sensor_enabled()
134 hw_set_bits(&adc_hw->cs, ADC_CS_START_ONCE_BITS); in adc_read()
149 hw_set_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS); in adc_run()
/external/platform/pico/rp2_common/hardware_spi/include/hardware/
A Dspi.h197 hw_set_bits(&spi_get_hw(spi)->cr1, enable_mask); in spi_set_format()
215 hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS); in spi_set_slave()
220 hw_set_bits(&spi_get_hw(spi)->cr1, enable_mask); in spi_set_slave()
/external/platform/pico/rp2_common/hardware_pio/include/hardware/
A Dpio.h583 hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_SM_RESTART_LSB + sm)); in pio_sm_restart()
598 hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS); in pio_restart_sm_mask()
625 hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm)); in pio_sm_clkdiv_restart()
660 hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS); in pio_clkdiv_restart_sm_mask()
677 hw_set_bits(&pio->ctrl, in pio_enable_sm_mask_in_sync()
711 hw_set_bits(&pio->inte0, 1u << source); in pio_set_irq0_source_enabled()
727 hw_set_bits(&pio->inte1, 1u << source); in pio_set_irq1_source_enabled()
743 hw_set_bits(&pio->inte0, source_mask); in pio_set_irq0_source_mask_enabled()
760 hw_set_bits(&pio->inte1, source_mask); in pio_set_irq1_source_mask_enabled()
/external/platform/pico/rp2_common/hardware_gpio/
A Dgpio.c24 hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); in gpio_get_pad()
99 hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS); in gpio_set_input_hysteresis_enabled()
171 hw_set_bits(en_reg, events); in _gpio_set_irq_enabled()
241 hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); in gpio_set_input_enabled()
/external/platform/pico/rp2_common/hardware_pwm/include/hardware/
A Dpwm.h364 hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_ADV_BITS); in pwm_advance_count()
381 hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_RET_BITS); in pwm_retard_count()
513 hw_set_bits(&pwm_hw->inte, 1u << slice_num); in pwm_set_irq_enabled()
530 hw_set_bits(&pwm_hw->inte, slice_mask); in pwm_set_irq_mask_enabled()
/external/platform/pico/rp2_common/hardware_spi/
A Dspi.c28 hw_set_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS); in spi_init()
31 hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); in spi_init()
70 hw_set_bits(&spi_get_hw(spi)->cr1, enable_mask); in spi_set_baudrate()
/external/platform/pico/rp2_common/hardware_resets/include/hardware/
A Dresets.h71 hw_set_bits(&resets_hw->reset, bits); in reset_block()
/external/platform/pico/rp2_common/hardware_timer/
A Dtimer.c163 hw_set_bits(&timer_hw->inte, 1u << alarm_num); in hardware_alarm_set_callback()
240 hw_set_bits(&timer_hw->intf, 1u << alarm_num); in hardware_alarm_force_irq()
/external/platform/pico/rp2_common/hardware_xosc/
A Dxosc.c37 hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB); in xosc_init()
/external/platform/pico/rp2_common/hardware_clocks/
A Dclocks.c108 hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); in clock_configure()
257 hw_set_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS); in clocks_handle_resus()
/external/platform/pico/rp2_common/hardware_base/include/hardware/
A Daddress_mapped.h121 __force_inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { in hw_set_bits() function
/external/platform/pico/rp2_common/hardware_uart/
A Duart.c58 hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_FEN_BITS); in uart_init()
/external/platform/pico/rp2_common/pico_cyw43_driver/
A Dcyw43_bus_pio_spi.c137 hw_set_bits(&bus_data->pio->input_sync_bypass, 1u << DATA_IN_PIN); in cyw43_spi_init()

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