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/external/platform/pico/rp2_common/pico_float/
A Dfloat_aeabi.S75 mov r0, r1
282 mvns r0, r0 @ carry inverse of r0 sign
283 adds r0, r0
307 sbcs r0, r0
343 sbcs r0, r0
379 negs r0, r0
393 negs r0, r0
451 cmn r0, r0
460 negs r0, r0
525 cmn r0, r0
[all …]
A Dfloat_v1_rom_shim.S47 ldrh r0, [r0, #2]
52 ldr r0, [r0]
71 orrs r5,r0
84 movs r5,r0
95 lsls r0,#7
99 movs r5,r0
100 movs r0,r1
119 mov r4,r0
120 mov r0,r1
126 lsls r0,r0,#5 @ Q28
[all …]
/external/platform/nrfx/mdk/
A Dses_startup_nrf_common.s119 bics r0, r1
120 mov sp, r0
126 blx r0
131 blx r0
140 cmp r0, r1
142 ldr r3, [r0]
144 adds r0, r0, #4
158 str r1, [r0]
164 ldr r1, [r0]
180 cmp r0, r1
[all …]
A Dgcc_startup_nrf51.S173 ldr r0, [r1,r3]
174 str r0, [r2,r3]
194 movs r0, 0
201 str r0, [r1, r2]
A Dgcc_startup_nrf5340_network.S256 ldr r0, [r1,r3]
257 str r0, [r2,r3]
277 movs r0, 0
284 str r0, [r1, r2]
A Dgcc_startup_nrf52805.S239 ldr r0, [r1,r3]
240 str r0, [r2,r3]
260 movs r0, 0
267 str r0, [r1, r2]
/external/platform/pico/rp2_common/pico_double/
A Ddouble_aeabi.S65 adds r0, r2
68 adds r0, r2
70 pop {r0, r2}
74 mov r0, r2
300 movs r0,#0
324 cmp r2,r0
331 cmp r0,r2
336 orrs r3,r0
363 sbcs r0, r0
399 sbcs r0, r0
[all …]
A Ddouble_v1_rom_shim.S52 ldrh r0, [r0, #2]
57 ldr r0, [r0]
86 movs r0,#\k
88 pop {r0-r3}
95 pop {r0}
96 mov r14,r0
97 pop {r0-r3}
217 mvns r0,r0
228 cmp r0,#0
232 adcs r0,r0
[all …]
/external/platform/pico/rp2_common/boot_stage2/
A Dboot2_w25q080.S108 ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
110 bics r0, r1
111 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
153 movs r0, #CMD_READ_STATUS2
156 cmp r0, r2
170 movs r0, #0
171 str r0, [r3, #SSI_DR0_OFFSET]
181 movs r0, #CMD_READ_STATUS
184 tst r0, r1
224 str r1, [r0]
[all …]
A Dboot2_at25sf128a.S108 ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
110 bics r0, r1
111 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
112 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
113 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
153 movs r0, #CMD_READ_STATUS2
156 cmp r0, r2
179 movs r0, #CMD_READ_STATUS
182 tst r0, r1
222 str r1, [r0]
[all …]
A Dboot2_is25lp080.S115 ldr r0, =CMD_READ_STATUS
118 cmp r0, r2
132 movs r0, #0
141 ldr r0, =CMD_READ_STATUS
144 tst r0, r1
192 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
193 str r1, [r0]
235 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
236 str r1, [r0]
A Dboot2_w25x10cl.S127 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
128 str r1, [r0]
143 ldr r0, [r3, #SSI_SR_OFFSET] // Read status register
144 tst r0, r1 // RFNE status flag set?
176 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
177 str r1, [r0]
A Dboot2_usb_blinky.S30 ldrh r0, [r7, #0] // Offset 0 is 16 bit pointer to function table
34 cmp r0, #0
37 mov r7, r0
38 ldr r0, =(1u << ACTIVITY_LED) // Mask of which GPIO (or GPIOs) to use
/external/platform/pico/rp2_common/pico_divider/
A Ddivider.S196 mvns r0, r0
289 dneg r0,r1
308 mvns r0,r0
468 @ r0:r1 y
531 @ r0 y
552 lsls r0,r5 @ r0:r1 is quh<<(4+xsh)
572 @ r0:r1 y
601 lsls r0,r5 @ r0:r1 is quh<<(4+xsh)
690 @ r0:r1 y
765 @ r0:r1 y
[all …]
/external/platform/nrfx/soc/
A Dnrfx_atomic_internal.h57 mov r4, r0 in nrfx_atomic_internal_mov()
60 ldrex r0, [r4] in nrfx_atomic_internal_mov()
77 mov r4, r0 in nrfx_atomic_internal_orr()
80 ldrex r0, [r4] in nrfx_atomic_internal_orr()
96 mov r4, r0 in nrfx_atomic_internal_and()
115 mov r4, r0 in nrfx_atomic_internal_eor()
134 mov r4, r0 in nrfx_atomic_internal_add()
153 mov r4, r0 in nrfx_atomic_internal_sub()
214 mov r4, r0 in nrfx_atomic_internal_sub_hs()
218 cmp r0, r1 in nrfx_atomic_internal_sub_hs()
[all …]
/external/platform/pico/rp2_common/boot_stage2/asminclude/boot2_helpers/
A Dexit_from_boot2.S16 pop {r0}
17 cmp r0, #0
19 bx r0
21 ldr r0, =(XIP_BASE + 0x100)
23 str r0, [r1]
24 ldmia r0, {r0, r1}
25 msr msp, r0
A Dwait_ssi_ready.S11 push {r0, r1, lr}
17 movs r0, #SSI_SR_TFE_BITS
18 tst r1, r0
20 movs r0, #SSI_SR_BUSY_BITS
21 tst r1, r0
24 pop {r0, r1, pc}
A Dread_flash_sreg.S19 str r0, [r3, #SSI_DR0_OFFSET]
21 str r0, [r3, #SSI_DR0_OFFSET]
25 ldr r0, [r3, #SSI_DR0_OFFSET]
26 ldr r0, [r3, #SSI_DR0_OFFSET]
/external/platform/pico/rp2_common/pico_int64_ops/
A Dpico_int64_ops_aeabi.S23 muls r3, r0
27 uxth r3, r0
30 lsrs r4, r0, #16
33 uxth r0, r0
34 muls r0, r2
38 adds r0, r4
43 adds r0, r3
/external/platform/pico/rp2_common/pico_standard_link/
A Dcrt0.S150 mrs r0, ipsr
151 subs r0, #16
203 movs r0, #0
206 str r0, [r1]
224 ldr r0, [r0]
225 cmp r0, #0
246 movs r0, #0
249 stm r1!, {r0}
271 ldm r1!, {r0}
272 stm r2!, {r0}
[all …]
/external/platform/pico/rp2_common/pico_bit_ops/
A Dbit_ops_aeabi.S36 ldr r0, =aeabi_bits_funcs
75 adds r0, #32
78 mov r0, r1
85 cmp r0, #0
90 mov r0, r1
92 adds r0, #32
101 mov ip, r0
102 pop {r0, r3}
105 add r0, r1
128 mov ip, r0 // reverse32 preserves ip
[all …]
/external/platform/pico/rp2_common/hardware_irq/
A Dirq_handler_chain.S57 push {r0, lr} // Save EXC_RETURN token, so `pop {r0, pc}` will return from interrupt
60 ldr r0, [r1, #4] // Get `handler` field of irq_handler_chain_slot
63 bx r0 // Enter handler
66 mov r0, lr // Get start of struct. This function was called by a bl at offset +4,
67 subs r0, #9 // so lr points to offset +8. Note also lr has its Thumb bit set!
70 pop {r0, pc} // Top of stack is EXC_RETURN
/external/platform/pico/rp2_common/hardware_divider/
A Ddivider.S10 str r0, [r3, #SIO_DIV_SDIVIDEND_OFFSET]
18 str r0, [r3, #SIO_DIV_UDIVIDEND_OFFSET]
32 ldr r0, [r3, #SIO_DIV_QUOTIENT_OFFSET]
39 stmia r0!, {r1-r2}
44 stmia r0!, {r1-r2}
49 ldmia r0!, {r1-r2}
52 ldmia r0!, {r1-r2}
/external/platform/stellaris/ti-driverlib/driverlib/
A Dcpu.c98 mrs r0, PRIMASK; in CPUcpsid() local
178 mrs r0, PRIMASK; in CPUprimask() local
258 mrs r0, PRIMASK; in CPUcpsie() local
367 msr BASEPRI, r0; in CPUbasepriSet() local
434 mrs r0, BASEPRI; in CPUbasepriGet() local
/external/platform/cc13xx/cc13xxware/driverlib/
A Dcpu.c91 mrs r0, PRIMASK; in CPUcpsid() local
168 mrs r0, PRIMASK; in CPUprimask() local
243 mrs r0, PRIMASK; in CPUcpsie() local
320 mrs r0, BASEPRI; in CPUbasepriGet() local
392 subs r0, #1; in CPUdelay() local

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