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Searched refs:GIC_DIST_CONFIG (Results 1 – 4 of 4) sorted by relevance

/platform/mediatek/mt6735/
A Dinterrupts.c87 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_CONFIG + i * 4 / 16, 0); in mt_gic_dist_init()
200 config = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4); in mt_irq_set_sens()
202 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config); in mt_irq_set_sens()
204 config = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4); in mt_irq_set_sens()
206 DRV_WriteReg32( GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config); in mt_irq_set_sens()
/platform/mediatek/mt6797/include/platform/
A Dmt_irq.h20 #define GIC_DIST_CONFIG 0xc00 macro
/platform/mediatek/common/gic/
A Dmt_gic_v3.c142 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_CONFIG + i * 4 / 16, 0); in mt_gic_dist_init()
256 config = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4); in mt_irq_set_sens()
258 DRV_WriteReg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config); in mt_irq_set_sens()
260 config = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4); in mt_irq_set_sens()
262 DRV_WriteReg32( GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config); in mt_irq_set_sens()
377 reg = DRV_Reg32(GIC_DIST_BASE + GIC_DIST_CONFIG + i * 4 / 16); in mt_irq_register_dump()
/platform/mediatek/mt6735/include/platform/
A Dmt_irq.h54 #define GIC_DIST_CONFIG 0xc00 macro

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