1 /* 2 * Copyright (c) 2015 Travis Geiselbrecht 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 #pragma once 9 10 #define SDRAM_BASE 0 11 /* Note: BCM2836/BCM2837 use different peripheral base than BCM2835 */ 12 #define BCM_PERIPH_BASE_PHYS (0x3f000000U) 13 #define BCM_PERIPH_SIZE (0x01100000U) 14 15 #if BCM2836 16 #define BCM_PERIPH_BASE_VIRT (0xe0000000U) 17 #elif BCM2837 18 #define BCM_PERIPH_BASE_VIRT (0xffffffffc0000000ULL) 19 #define MEMORY_APERTURE_SIZE (1024 * 1024 * 1024) 20 #else 21 #error Unknown BCM28XX Variant 22 #endif 23 24 #define BCM_SDRAM_BUS_ADDR_BASE_NO_L2 0xc0000000 25 #define BCM_SDRAM_BUS_ADDR_BASE (BCM_SDRAM_BUS_ADDR_BASE_NO_L2) 26 27 /* pointer to 'local' peripherals at 0x40000000 */ 28 #define BCM_LOCAL_PERIPH_BASE_VIRT (BCM_PERIPH_BASE_VIRT + 0x01000000) 29 30 #define IC0_BASE (BCM_PERIPH_BASE_VIRT + 0x2000) 31 #define ST_BASE (BCM_PERIPH_BASE_VIRT + 0x3000) 32 #define MPHI_BASE (BCM_PERIPH_BASE_VIRT + 0x6000) 33 #define DMA_BASE (BCM_PERIPH_BASE_VIRT + 0x7000) 34 #define ARM_BASE (BCM_PERIPH_BASE_VIRT + 0xB000) 35 #define PM_BASE (BCM_PERIPH_BASE_VIRT + 0x100000) 36 #define PCM_CLOCK_BASE (BCM_PERIPH_BASE_VIRT + 0x101098) 37 #define RNG_BASE (BCM_PERIPH_BASE_VIRT + 0x104000) 38 #define GPIO_BASE (BCM_PERIPH_BASE_VIRT + 0x200000) 39 #define UART0_BASE (BCM_PERIPH_BASE_VIRT + 0x201000) 40 #define MMCI0_BASE (BCM_PERIPH_BASE_VIRT + 0x202000) 41 #define I2S_BASE (BCM_PERIPH_BASE_VIRT + 0x203000) 42 #define SPI0_BASE (BCM_PERIPH_BASE_VIRT + 0x204000) 43 #define BSC0_BASE (BCM_PERIPH_BASE_VIRT + 0x205000) 44 #define AUX_BASE (BCM_PERIPH_BASE_VIRT + 0x215000) 45 #define MINIUART_BASE (BCM_PERIPH_BASE_VIRT + 0x215040) 46 #define EMMC_BASE (BCM_PERIPH_BASE_VIRT + 0x300000) 47 #define SMI_BASE (BCM_PERIPH_BASE_VIRT + 0x600000) 48 #define BSC1_BASE (BCM_PERIPH_BASE_VIRT + 0x804000) 49 #define USB_BASE (BCM_PERIPH_BASE_VIRT + 0x980000) 50 #define MCORE_BASE (BCM_PERIPH_BASE_VIRT + 0x0000) 51 52 #define ARMCTRL_BASE (ARM_BASE + 0x000) 53 #define ARMCTRL_INTC_BASE (ARM_BASE + 0x200) 54 #define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) 55 #define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) 56 57 /* Videocore (GPU) mailbox registers for core0 */ 58 #define ARM0_MAILBOX_BASE (ARM_BASE + 0x0880) 59 #define ARM0_MAILBOX_READ (ARM0_MAILBOX_BASE + 0x00) 60 #define ARM0_MAILBOX_PEEK (ARM0_MAILBOX_BASE + 0x10) 61 #define ARM0_MAILBOX_CONFIG (ARM0_MAILBOX_BASE + 0x1C) 62 #define ARM0_MAILBOX_STATUS (ARM0_MAILBOX_BASE + 0x18) 63 #define ARM0_MAILBOX_WRITE (ARM0_MAILBOX_BASE + 0x20) 64 65 #define ARM_LOCAL_BASE (BCM_LOCAL_PERIPH_BASE_VIRT) 66 67 /* interrupts */ 68 #define ARM_IRQ1_BASE 0 69 #define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) 70 #define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) 71 #define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) 72 #define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) 73 #define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) 74 #define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) 75 #define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) 76 #define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) 77 #define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) 78 #define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) 79 #define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) 80 #define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) 81 #define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) 82 #define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) 83 #define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) 84 #define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) 85 #define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) 86 #define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) 87 #define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) 88 #define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) 89 #define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) 90 #define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) 91 #define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) 92 #define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) 93 #define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) 94 #define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) 95 #define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) 96 #define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) 97 #define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) 98 #define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) 99 #define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) 100 #define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) 101 102 #define ARM_IRQ2_BASE 32 103 #define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) 104 #define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) 105 #define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) 106 #define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) 107 #define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) 108 #define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) 109 #define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) 110 #define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) 111 #define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) 112 #define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) 113 #define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) 114 #define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) 115 #define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) 116 #define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) 117 #define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) 118 #define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) 119 #define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) 120 #define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) 121 #define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) 122 #define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) 123 #define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) 124 #define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) 125 #define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) 126 #define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) 127 #define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) 128 #define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) 129 #define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) 130 #define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) 131 #define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) 132 #define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) 133 #define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) 134 #define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) 135 136 /* ARM interrupts, which are mostly mirrored from bank 1 and 2 */ 137 #define ARM_IRQ0_BASE 64 138 #define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) 139 #define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) 140 #define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) 141 #define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) 142 #define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) 143 #define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) 144 #define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) 145 #define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) 146 #define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) 147 #define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) 148 #define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) 149 #define INTERRUPT_USB (ARM_IRQ0_BASE + 11) 150 #define INTERRUPT_3D (ARM_IRQ0_BASE + 12) 151 #define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) 152 #define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) 153 #define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) 154 #define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) 155 #define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) 156 #define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) 157 #define INTERRUPT_UART (ARM_IRQ0_BASE + 19) 158 #define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) 159 160 #define ARM_IRQ_LOCAL_BASE 96 161 #define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0) 162 #define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1) 163 #define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2) 164 #define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3) 165 #define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4) 166 #define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5) 167 #define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6) 168 #define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7) 169 #define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8) 170 #define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9) 171 #define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10) 172 #define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11) 173 174 #define MAX_INT INTERRUPT_ARM_LOCAL_TIMER 175 176 /* GPIO */ 177 178 #define GPIO_GPFSEL0 (GPIO_BASE + 0x00) 179 #define GPIO_GPFSEL1 (GPIO_BASE + 0x04) 180 #define GPIO_GPFSEL2 (GPIO_BASE + 0x08) 181 #define GPIO_GPFSEL3 (GPIO_BASE + 0x0C) 182 #define GPIO_GPFSEL4 (GPIO_BASE + 0x10) 183 #define GPIO_GPFSEL5 (GPIO_BASE + 0x14) 184 #define GPIO_GPSET0 (GPIO_BASE + 0x1C) 185 #define GPIO_GPSET1 (GPIO_BASE + 0x20) 186 #define GPIO_GPCLR0 (GPIO_BASE + 0x28) 187 #define GPIO_GPCLR1 (GPIO_BASE + 0x2C) 188 #define GPIO_GPLEV0 (GPIO_BASE + 0x34) 189 #define GPIO_GPLEV1 (GPIO_BASE + 0x38) 190 #define GPIO_GPEDS0 (GPIO_BASE + 0x40) 191 #define GPIO_GPEDS1 (GPIO_BASE + 0x44) 192 #define GPIO_GPREN0 (GPIO_BASE + 0x4C) 193 #define GPIO_GPREN1 (GPIO_BASE + 0x50) 194 #define GPIO_GPFEN0 (GPIO_BASE + 0x58) 195 #define GPIO_GPFEN1 (GPIO_BASE + 0x5C) 196 #define GPIO_GPHEN0 (GPIO_BASE + 0x64) 197 #define GPIO_GPHEN1 (GPIO_BASE + 0x68) 198 #define GPIO_GPLEN0 (GPIO_BASE + 0x70) 199 #define GPIO_GPLEN1 (GPIO_BASE + 0x74) 200 #define GPIO_GPAREN0 (GPIO_BASE + 0x7C) 201 #define GPIO_GPAREN1 (GPIO_BASE + 0x80) 202 #define GPIO_GPAFEN0 (GPIO_BASE + 0x88) 203 #define GPIO_GPAFEN1 (GPIO_BASE + 0x8C) 204 #define GPIO_GPPUD (GPIO_BASE + 0x94) 205 #define GPIO_GPPUDCLK0 (GPIO_BASE + 0x98) 206 #define GPIO_GPPUDCLK1 (GPIO_BASE + 0x9C) 207