1 /* 2 * Copyright (c) 2014 Travis Geiselbrecht 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 #pragma once 9 10 #include <lk/reg.h> 11 12 /* common address space regions */ 13 #define FPGASLAVES_BASE (0xc0000000) 14 #define PERIPH_BASE (0xfc000000) 15 #define LWPFGASLAVES_BASE (0xff200000) 16 17 /* hardware base addresses */ 18 #define STM_BASE (0xfc000000) 19 #define DAP_BASE (0xff000000) 20 #define EMAC0_BASE (0xff700000) 21 #define EMAC1_BASE (0xff702000) 22 #define SDMMC_BASE (0xff704000) 23 #define QSPI_BASE (0xff705000) 24 #define FPGAMGRREGS_BASE (0xff706000) 25 #define ACPIDMAP_BASE (0xff707000) 26 #define GPIO0_BASE (0xff708000) 27 #define GPIO1_BASE (0xff709000) 28 #define GPIO2_BASE (0xff70a000) 29 #define L3REGS_BASE (0xff800000) 30 #define NANDDATA_BASE (0xff900000) 31 #define QSPIDATA_BASE (0xffa00000) 32 #define USB0_BASE (0xffb00000) 33 #define USB1_BASE (0xffb40000) 34 #define NANDREGS_BASE (0xffb80000) 35 #define FPGAMGRDATA_BASE (0xffb90000) 36 #define CAN0_BASE (0xffc00000) 37 #define CAN1_BASE (0xffc01000) 38 #define UART0_BASE (0xffc02000) 39 #define UART1_BASE (0xffc03000) 40 #define I2C0_BASE (0xffc04000) 41 #define I2C1_BASE (0xffc05000) 42 #define I2C2_BASE (0xffc06000) 43 #define I2C3_BASE (0xffc07000) 44 #define SPTIMER0_BASE (0xffc08000) 45 #define SPTIMER1_BASE (0xffc09000) 46 #define SDRREGS_BASE (0xffc20000) 47 #define OSC1TIMER0_BASE (0xffd00000) 48 #define OSC1TIMER1_BASE (0xffd01000) 49 #define L4WD0_BASE (0xffd02000) 50 #define L4WD1_BASE (0xffd03000) 51 #define CLKMGR_BASE (0xffd04000) 52 #define RSTMGR_BASE (0xffd05000) 53 #define SYSMGR_BASE (0xffd08000) 54 #define DMANONSECURE_BASE (0xffe00000) 55 #define DMASECURE_BASE (0xffe01000) 56 #define SPIS0_BASE (0xffe02000) 57 #define SPIS1_BASE (0xffe03000) 58 #define SPIM0_BASE (0xfff00000) 59 #define SPIM1_BASE (0xfff01000) 60 #define SCANMGR_BASE (0xfff02000) 61 #define ROM_BASE (0xfffd0000) 62 #define MPUSCU_BASE (0xfffec000) 63 #define MPUL2_BASE (0xfffef000) 64 #define OCRAM_BASE (0xffff0000) 65 66 #define CPUPRIV_BASE (MPUSCU_BASE) 67 #define SCU_CONTROL_BASE (CPUPRIV_BASE + 0x0000) 68 #define GIC_PROC_BASE (CPUPRIV_BASE + 0x0100) 69 #define GLOBAL_TIMER_BASE (CPUPRIV_BASE + 0x0200) 70 #define PRIV_TIMER_BASE (CPUPRIV_BASE + 0x0600) 71 #define GIC_DISTRIB_BASE (CPUPRIV_BASE + 0x1000) 72 73 /* interrupts */ 74 75 #define FPGA_INT(n) (72 + (n)) 76 77 #define SPI0_INT 186 78 #define SPI1_INT 187 79 #define SPI2_INT 188 80 #define SPI3_INT 189 81 #define I2C0_INT 190 82 #define I2C1_INT 191 83 #define I2C2_INT 192 84 #define I2C3_INT 193 85 #define UART0_INT 194 86 #define UART1_INT 195 87 #define GPIO0_INT 196 88 #define GPIO1_INT 197 89 #define GPIO2_INT 198 90 #define TIMER_L4SP0_INT 199 91 #define TIMER_L4SP1_INT 200 92 #define TIMER_OSC0_INT 201 93 #define TIMER_OSC1_INT 202 94 #define WDOG0_INT 203 95 #define WDOG1_INT 204 96 #define CLKMGR_INT 205 97 #define MPUWAKEUP_INT 206 98 #define FPGA_MAN_INT 207 99 100 #define MAX_INT 212 101 102