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Searched refs:divisor2 (Results 1 – 2 of 2) sorted by relevance

/platform/zynq/
A Dclocks.c245 …q_periph periph, bool enable, enum zynq_clock_source source, uint32_t divisor, uint32_t divisor2) { in zynq_set_clock() argument
263 ctrl = (ctrl & ~(0x3f << 20)) | (divisor2 << 20); in zynq_set_clock()
326 uint32_t divisor2 = 1; in zynq_get_clock() local
328 divisor2 = BITS_SHIFT(*REG32(clk_reg), 25, 20); in zynq_get_clock()
329 if (divisor2 == 0) in zynq_get_clock()
333 uint32_t clk = srcclk / divisor / divisor2; in zynq_get_clock()
/platform/zynq/include/platform/
A Dzynq.h560 …_clock(enum zynq_periph, bool enable, enum zynq_clock_source, uint32_t divisor, uint32_t divisor2);

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