1 /*
2  * Copyright (c) 2008 Travis Geiselbrecht
3  *
4  * Use of this source code is governed by a MIT-style
5  * license that can be found in the LICENSE file or at
6  * https://opensource.org/licenses/MIT
7  */
8 #ifndef __ARCH_CPU_H
9 #define __ARCH_CPU_H
10 
11 /* arm specific stuff */
12 #define PAGE_SIZE 4096
13 #define PAGE_SIZE_SHIFT 12
14 
15 #if ARM_CPU_ARM7
16 /* irrelevant, no consistent cache */
17 #define CACHE_LINE 32
18 #elif ARM_CPU_ARM926
19 #define CACHE_LINE 32
20 #elif ARM_CPU_ARM1136
21 #define CACHE_LINE 32
22 #elif ARM_CPU_ARMEMU
23 #define CACHE_LINE 32
24 #elif ARM_CPU_CORTEX_A7
25 #define CACHE_LINE 64 /* XXX L1 icache is 32 bytes */
26 #elif ARM_CPU_CORTEX_A8
27 #define CACHE_LINE 64
28 #elif ARM_CPU_CORTEX_A9
29 #define CACHE_LINE 32
30 #elif ARM_CPU_CORTEX_M0 || ARM_CPU_CORTEX_M0_PLUS || ARM_CPU_CORTEX_M3 || ARM_CPU_CORTEX_M4
31 #define CACHE_LINE 32 /* doesn't actually matter */
32 #elif ARM_CPU_CORTEX_M55
33 #define CACHE_LINE 32
34 #elif ARM_CPU_CORTEX_M7
35 #define CACHE_LINE 32
36 #elif ARM_CPU_CORTEX_A15
37 #define CACHE_LINE 64
38 #elif ARM_CPU_CORTEX_R4F
39 #define CACHE_LINE 64
40 #else
41 #error unknown cpu
42 #endif
43 
44 #endif
45 
46