1 /******************************************************************************
2 * Filename: cpu.h
3 * Revised: 2015-10-28 15:51:56 +0100 (Wed, 28 Oct 2015)
4 * Revision: 44872
5 *
6 * Description: Defines and prototypes for the CPU instruction wrapper
7 * functions.
8 *
9 * Copyright (c) 2015, Texas Instruments Incorporated
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1) Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2) Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may
23 * be used to endorse or promote products derived from this software without
24 * specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 *
38 ******************************************************************************/
39
40 //*****************************************************************************
41 //
42 //! \addtogroup system_cpu_group
43 //! @{
44 //! \addtogroup cpu_api
45 //! @{
46 //
47 //*****************************************************************************
48
49 #ifndef __CPU_H__
50 #define __CPU_H__
51
52 //*****************************************************************************
53 //
54 // If building with a C++ compiler, make all of the definitions in this header
55 // have a C binding.
56 //
57 //*****************************************************************************
58 #ifdef __cplusplus
59 extern "C"
60 {
61 #endif
62
63 #include <stdbool.h>
64 #include <stdint.h>
65 #include <inc/hw_types.h>
66 #include <inc/hw_memmap.h>
67 #include <inc/hw_cpu_scs.h>
68
69 //*****************************************************************************
70 //
71 // Support for DriverLib in ROM:
72 // This section renames all functions that are not "static inline", so that
73 // calling these functions will default to implementation in flash. At the end
74 // of this file a second renaming will change the defaults to implementation in
75 // ROM for available functions.
76 //
77 // To force use of the implementation in flash, e.g. for debugging:
78 // - Globally: Define DRIVERLIB_NOROM at project level
79 // - Per function: Use prefix "NOROM_" when calling the function
80 //
81 //*****************************************************************************
82 #if !defined(DOXYGEN)
83 #define CPUcpsid NOROM_CPUcpsid
84 #define CPUprimask NOROM_CPUprimask
85 #define CPUcpsie NOROM_CPUcpsie
86 #define CPUbasepriGet NOROM_CPUbasepriGet
87 #define CPUdelay NOROM_CPUdelay
88 #endif
89
90 //*****************************************************************************
91 //
92 // API Functions and prototypes
93 //
94 //*****************************************************************************
95
96 //*****************************************************************************
97 //
98 //! \brief Disable all external interrupts.
99 //!
100 //! Use this function to disable all system interrupts. This function is
101 //! implemented as a wrapper function for the CPSID instruction.
102 //!
103 //! \return Returns the state of \b PRIMASK on entry
104 //
105 //*****************************************************************************
106 extern uint32_t CPUcpsid(void);
107
108 //*****************************************************************************
109 //
110 //! \brief Get the current interrupt state.
111 //!
112 //! Use this function to retrieve the current state of the interrupts. This
113 //! function is implemented as a wrapper function returning the state of
114 //! PRIMASK.
115 //!
116 //! \return Returns the state of the \b PRIMASK (indicating whether interrupts
117 //! are enabled or disabled).
118 //
119 //*****************************************************************************
120 extern uint32_t CPUprimask(void);
121
122 //*****************************************************************************
123 //
124 //! \brief Enable all external interrupts.
125 //!
126 //! Use this function to enable all system interrupts. This function is
127 //! implemented as a wrapper function for the CPSIE instruction.
128 //!
129 //! \return Returns the state of \b PRIMASK on entry.
130 //
131 //*****************************************************************************
132 extern uint32_t CPUcpsie(void);
133
134 //*****************************************************************************
135 //
136 //! \brief Wait for interrupt.
137 //!
138 //! Use this function to let the System CPU wait for the next interrupt. This
139 //! function is implemented as a wrapper function for the WFI instruction.
140 //!
141 //! \return None
142 //
143 //*****************************************************************************
144 #if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN)
145 __STATIC_INLINE void
CPUwfi(void)146 CPUwfi(void)
147 {
148 //
149 // Wait for the next interrupt.
150 //
151 __asm(" wfi\n");
152 }
153 #elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
154 __asm __STATIC_INLINE void
CPUwfi(void)155 CPUwfi(void)
156 {
157 //
158 // Wait for the next interrupt.
159 //
160 wfi;
161 bx lr
162 }
163 #elif defined(__TI_COMPILER_VERSION__)
164 __STATIC_INLINE void
CPUwfi(void)165 CPUwfi(void)
166 {
167 //
168 // Wait for the next interrupt.
169 //
170 __asm(" wfi\n");
171 }
172 #else
173 __STATIC_INLINE void __attribute__((always_inline))
CPUwfi(void)174 CPUwfi(void)
175 {
176 //
177 // Wait for the next interrupt.
178 //
179 __asm(" wfi\n");
180 }
181 #endif
182
183 //*****************************************************************************
184 //
185 //! \brief Wait for event.
186 //!
187 //! Use this function to let the System CPU wait for the next event. This
188 //! function is implemented as a wrapper function for the WFE instruction.
189 //!
190 //! \return None
191 //
192 //*****************************************************************************
193 #if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN)
194 __STATIC_INLINE void
CPUwfe(void)195 CPUwfe(void)
196 {
197 //
198 // Wait for the next event.
199 //
200 __asm(" wfe\n");
201 }
202 #elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
203 __asm __STATIC_INLINE void
CPUwfe(void)204 CPUwfe(void)
205 {
206 //
207 // Wait for the next event.
208 //
209 wfe;
210 bx lr
211 }
212 #elif defined(__TI_COMPILER_VERSION__)
213 __STATIC_INLINE void
CPUwfe(void)214 CPUwfe(void)
215 {
216 //
217 // Wait for the next event.
218 //
219 __asm(" wfe\n");
220 }
221 #else
222 __STATIC_INLINE void __attribute__((always_inline))
CPUwfe(void)223 CPUwfe(void)
224 {
225 //
226 // Wait for the next event.
227 //
228 __asm(" wfe\n");
229 }
230 #endif
231
232 //*****************************************************************************
233 //
234 //! \brief Send event.
235 //!
236 //! Use this function to let the System CPU send an event. This function is
237 //! implemented as a wrapper function for the SEV instruction.
238 //!
239 //! \return None
240 //
241 //*****************************************************************************
242 #if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN)
243 __STATIC_INLINE void
CPUsev(void)244 CPUsev(void)
245 {
246 //
247 // Send event.
248 //
249 __asm(" sev\n");
250 }
251 #elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
252 __asm __STATIC_INLINE void
CPUsev(void)253 CPUsev(void)
254 {
255 //
256 // Send event.
257 //
258 sev;
259 bx lr
260 }
261 #elif defined(__TI_COMPILER_VERSION__)
262 __STATIC_INLINE void
CPUsev(void)263 CPUsev(void)
264 {
265 //
266 // Send event.
267 //
268 __asm(" sev\n");
269 }
270 #else
271 __STATIC_INLINE void __attribute__((always_inline))
CPUsev(void)272 CPUsev(void)
273 {
274 //
275 // Send event.
276 //
277 __asm(" sev\n");
278 }
279 #endif
280
281
282 //*****************************************************************************
283 //
284 //! \brief Update the interrupt priority disable level.
285 //!
286 //! Use this function to change the level of priority that will disable
287 //! interrupts with a lower priority level.
288 //!
289 //! \param ui32NewBasepri is the new basis priority level to set.
290 //!
291 //! \return None
292 //
293 //*****************************************************************************
294 #if defined(__IAR_SYSTEMS_ICC__) || defined(DOXYGEN)
295 __STATIC_INLINE void
CPUbasepriSet(uint32_t ui32NewBasepri)296 CPUbasepriSet(uint32_t ui32NewBasepri)
297 {
298 //
299 // Set the BASEPRI register.
300 //
301 __asm(" msr BASEPRI, r0\n");
302 }
303 #elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
304 __asm __STATIC_INLINE void
CPUbasepriSet(uint32_t ui32NewBasepri)305 CPUbasepriSet(uint32_t ui32NewBasepri)
306 {
307 //
308 // Set the BASEPRI register.
309 //
310 msr BASEPRI, r0;
311 bx lr
312 }
313 #elif defined(__TI_COMPILER_VERSION__)
314 __STATIC_INLINE void
CPUbasepriSet(uint32_t ui32NewBasepri)315 CPUbasepriSet(uint32_t ui32NewBasepri)
316 {
317 //
318 // Set the BASEPRI register.
319 //
320 __asm(" msr BASEPRI, r0\n");
321 }
322 #else
323 #pragma GCC diagnostic push
324 #pragma GCC diagnostic ignored "-Wattributes"
325 __STATIC_INLINE void __attribute__ ((naked))
CPUbasepriSet(uint32_t ui32NewBasepri)326 CPUbasepriSet(uint32_t ui32NewBasepri)
327 {
328 //
329 // Set the BASEPRI register.
330 //
331 __asm(" msr BASEPRI, r0\n"
332 " bx lr\n");
333 }
334 #pragma GCC diagnostic pop
335 #endif
336
337 //*****************************************************************************
338 //
339 //! \brief Get the interrupt priority disable level.
340 //!
341 //! Use this function to get the the level of priority that will disable
342 //! interrupts with a lower priority level.
343 //!
344 //! \return Returns the value of the \b BASEPRI register.
345 //
346 //*****************************************************************************
347 extern uint32_t CPUbasepriGet(void);
348
349 //*****************************************************************************
350 //
351 //! \brief Provide a small delay.
352 //!
353 //! This function provides means for generating a constant length delay. It
354 //! is written in assembly to keep the delay consistent across tool chains,
355 //! avoiding the need to tune the delay based on the tool chain in use.
356 //!
357 //! The loop takes 3 cycles/loop.
358 //!
359 //! \param ui32Count is the number of delay loop iterations to perform.
360 //!
361 //! \return None
362 //
363 //*****************************************************************************
364 extern void CPUdelay(uint32_t ui32Count);
365
366 //*****************************************************************************
367 //
368 //! \brief Disable CPU write buffering (recommended for debug purpose only).
369 //!
370 //! This function helps debugging "bus fault crashes".
371 //! Disables write buffer use during default memory map accesses.
372 //!
373 //! This causes all bus faults to be precise bus faults but decreases the
374 //! performance of the processor because the stores to memory have to complete
375 //! before the next instruction can be executed.
376 //!
377 //! \return None
378 //!
379 //! \sa \ref CPU_WriteBufferEnable()
380 //
381 //*****************************************************************************
382 __STATIC_INLINE void
CPU_WriteBufferDisable(void)383 CPU_WriteBufferDisable( void )
384 {
385 HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1;
386 }
387
388 //*****************************************************************************
389 //
390 //! \brief Enable CPU write buffering (default setting).
391 //!
392 //! Re-enables write buffer during default memory map accesses if
393 //! \ref CPU_WriteBufferDisable() has been used for bus fault debugging.
394 //!
395 //! \return None
396 //!
397 //! \sa \ref CPU_WriteBufferDisable()
398 //
399 //*****************************************************************************
400 __STATIC_INLINE void
CPU_WriteBufferEnable(void)401 CPU_WriteBufferEnable( void )
402 {
403 HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0;
404 }
405
406 //*****************************************************************************
407 //
408 // Support for DriverLib in ROM:
409 // Redirect to implementation in ROM when available.
410 //
411 //*****************************************************************************
412 #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
413 #include <driverlib/rom.h>
414 #ifdef ROM_CPUcpsid
415 #undef CPUcpsid
416 #define CPUcpsid ROM_CPUcpsid
417 #endif
418 #ifdef ROM_CPUprimask
419 #undef CPUprimask
420 #define CPUprimask ROM_CPUprimask
421 #endif
422 #ifdef ROM_CPUcpsie
423 #undef CPUcpsie
424 #define CPUcpsie ROM_CPUcpsie
425 #endif
426 #ifdef ROM_CPUbasepriGet
427 #undef CPUbasepriGet
428 #define CPUbasepriGet ROM_CPUbasepriGet
429 #endif
430 #ifdef ROM_CPUdelay
431 #undef CPUdelay
432 #define CPUdelay ROM_CPUdelay
433 #endif
434 #endif
435
436 //*****************************************************************************
437 //
438 // Mark the end of the C bindings section for C++ compilers.
439 //
440 //*****************************************************************************
441 #ifdef __cplusplus
442 }
443 #endif
444
445 #endif // __CPU_H__
446
447 //*****************************************************************************
448 //
449 //! Close the Doxygen group.
450 //! @}
451 //! @}
452 //
453 //*****************************************************************************
454