1 /* 2 3 Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. 4 5 Redistribution and use in source and binary forms, with or without 6 modification, are permitted provided that the following conditions are met: 7 8 1. Redistributions of source code must retain the above copyright notice, this 9 list of conditions and the following disclaimer. 10 11 2. Redistributions in binary form must reproduce the above copyright 12 notice, this list of conditions and the following disclaimer in the 13 documentation and/or other materials provided with the distribution. 14 15 3. Neither the name of Nordic Semiconductor ASA nor the names of its 16 contributors may be used to endorse or promote products derived from this 17 software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. 30 31 */ 32 33 #ifndef _NRF9160_PERIPHERALS_H 34 #define _NRF9160_PERIPHERALS_H 35 36 /* UICR */ 37 #define UICR_KEYSLOT_COUNT 128 38 39 /* Clock Peripheral */ 40 #define CLOCK_PRESENT 41 #define CLOCK_COUNT 1 42 43 /* Power Peripheral */ 44 #define POWER_PRESENT 45 #define POWER_COUNT 1 46 47 /* Non-Volatile Memory Controller */ 48 #define NVMC_PRESENT 49 #define NVMC_COUNT 1 50 51 #define NVMC_FEATURE_CACHE_PRESENT 52 53 /* GPIO */ 54 #define GPIO_PRESENT 55 #define GPIO_COUNT 1 56 57 #define P0_PIN_NUM 32 58 59 #define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL 60 61 /* Distributed Peripheral to Peripheral Interconnect */ 62 #define DPPI_PRESENT 63 #define DPPI_COUNT 1 64 65 #define DPPI_CH_NUM 16 66 #define DPPI_GROUP_NUM 6 67 68 /* Event Generator Unit */ 69 #define EGU_PRESENT 70 #define EGU_COUNT 6 71 72 #define EGU0_CH_NUM 16 73 #define EGU1_CH_NUM 16 74 #define EGU2_CH_NUM 16 75 #define EGU3_CH_NUM 16 76 #define EGU4_CH_NUM 16 77 #define EGU5_CH_NUM 16 78 79 /* Timer/Counter */ 80 #define TIMER_PRESENT 81 #define TIMER_COUNT 3 82 83 #define TIMER0_MAX_SIZE 32 84 #define TIMER1_MAX_SIZE 32 85 #define TIMER2_MAX_SIZE 32 86 87 88 #define TIMER0_CC_NUM 6 89 #define TIMER1_CC_NUM 6 90 #define TIMER2_CC_NUM 6 91 92 /* Real Time Counter */ 93 #define RTC_PRESENT 94 #define RTC_COUNT 2 95 96 #define RTC0_CC_NUM 4 97 #define RTC1_CC_NUM 4 98 99 /* Watchdog Timer */ 100 #define WDT_PRESENT 101 #define WDT_COUNT 1 102 103 /* Serial Peripheral Interface Master with DMA */ 104 #define SPIM_PRESENT 105 #define SPIM_COUNT 4 106 107 #define SPIM0_MAX_DATARATE 8 108 #define SPIM1_MAX_DATARATE 8 109 #define SPIM2_MAX_DATARATE 8 110 #define SPIM3_MAX_DATARATE 8 111 112 #define SPIM0_EASYDMA_MAXCNT_SIZE 12 113 #define SPIM1_EASYDMA_MAXCNT_SIZE 12 114 #define SPIM2_EASYDMA_MAXCNT_SIZE 12 115 #define SPIM3_EASYDMA_MAXCNT_SIZE 12 116 117 /* Serial Peripheral Interface Slave with DMA*/ 118 #define SPIS_PRESENT 119 #define SPIS_COUNT 4 120 121 #define SPIS0_EASYDMA_MAXCNT_SIZE 12 122 #define SPIS1_EASYDMA_MAXCNT_SIZE 12 123 #define SPIS2_EASYDMA_MAXCNT_SIZE 12 124 #define SPIS3_EASYDMA_MAXCNT_SIZE 12 125 126 /* Two Wire Interface Master with DMA */ 127 #define TWIM_PRESENT 128 #define TWIM_COUNT 4 129 130 #define TWIM0_EASYDMA_MAXCNT_SIZE 12 131 #define TWIM1_EASYDMA_MAXCNT_SIZE 12 132 #define TWIM2_EASYDMA_MAXCNT_SIZE 12 133 #define TWIM3_EASYDMA_MAXCNT_SIZE 12 134 135 /* Two Wire Interface Slave with DMA */ 136 #define TWIS_PRESENT 137 #define TWIS_COUNT 4 138 139 #define TWIS0_EASYDMA_MAXCNT_SIZE 12 140 #define TWIS1_EASYDMA_MAXCNT_SIZE 12 141 #define TWIS2_EASYDMA_MAXCNT_SIZE 12 142 #define TWIS3_EASYDMA_MAXCNT_SIZE 12 143 144 /* Universal Asynchronous Receiver-Transmitter with DMA */ 145 #define UARTE_PRESENT 146 #define UARTE_COUNT 4 147 148 #define UARTE0_EASYDMA_MAXCNT_SIZE 12 149 #define UARTE1_EASYDMA_MAXCNT_SIZE 12 150 #define UARTE2_EASYDMA_MAXCNT_SIZE 12 151 #define UARTE3_EASYDMA_MAXCNT_SIZE 12 152 153 /* Successive Approximation Analog to Digital Converter */ 154 #define SAADC_PRESENT 155 #define SAADC_COUNT 1 156 157 #define SAADC_CH_NUM 8 158 #define SAADC_EASYDMA_MAXCNT_SIZE 15 159 160 /* GPIO Tasks and Events */ 161 #define GPIOTE_PRESENT 162 #define GPIOTE_COUNT 2 163 164 #define GPIOTE_CH_NUM 8 165 166 #define GPIOTE_FEATURE_SET_PRESENT 167 #define GPIOTE_FEATURE_CLR_PRESENT 168 169 /* Pulse Width Modulator */ 170 #define PWM_PRESENT 171 #define PWM_COUNT 4 172 173 #define PWM_CH_NUM 4 174 175 #define PWM_EASYDMA_MAXCNT_SIZE 15 176 177 /* Pulse Density Modulator */ 178 #define PDM_PRESENT 179 #define PDM_COUNT 1 180 181 #define PDM_EASYDMA_MAXCNT_SIZE 15 182 183 /* Inter-IC Sound Interface */ 184 #define I2S_PRESENT 185 #define I2S_COUNT 1 186 187 #define I2S_EASYDMA_MAXCNT_SIZE 14 188 189 /* Inter Processor Communication */ 190 #define IPC_PRESENT 191 #define IPC_COUNT 1 192 193 #define IPC_CH_NUM 8 194 #define IPC_CONF_NUM 8 195 #define IPC_GPMEM_NUM 4 196 197 /* FPU */ 198 #define FPU_PRESENT 199 #define FPU_COUNT 1 200 201 /* SPU */ 202 #define SPU_PRESENT 203 #define SPU_COUNT 1 204 205 /* CRYPTOCELL */ 206 #define CRYPTOCELL_PRESENT 207 #define CRYPTOCELL_COUNT 1 208 209 /* KMU */ 210 #define KMU_PRESENT 211 #define KMU_COUNT 1 212 213 #define KMU_KEYSLOT_PRESENT 214 215 /* MAGPIO */ 216 #define MAGPIO_PRESENT 217 #define MAGPIO_COUNT 1 218 #define MAGPIO_PIN_NUM 3 219 220 /* REGULATORS */ 221 #define REGULATORS_PRESENT 222 #define REGULATORS_COUNT 1 223 224 225 #endif // _NRF9160_PERIPHERALS_H 226