1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /* 4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _HARDWARE_STRUCTS_PIO_H 10 #define _HARDWARE_STRUCTS_PIO_H 11 12 #include "hardware/address_mapped.h" 13 #include "hardware/regs/pio.h" 14 15 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio 16 // 17 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 18 // _REG_(x) will link to the corresponding register in hardware/regs/pio.h. 19 // 20 // Bit-field descriptions are of the form: 21 // BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION 22 23 typedef struct pio_sm_hw { 24 _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV 25 // Clock divisor register for state machine 0 26 // 0xffff0000 [31:16] : INT (1): Effective frequency is sysclk/(int + frac/256) 27 // 0x0000ff00 [15:8] : FRAC (0): Fractional part of clock divisor 28 io_rw_32 clkdiv; 29 30 _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL 31 // Execution/behavioural settings for state machine 0 32 // 0x80000000 [31] : EXEC_STALLED (0): If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine 33 // 0x40000000 [30] : SIDE_EN (0): If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable,... 34 // 0x20000000 [29] : SIDE_PINDIR (0): If 1, side-set data is asserted to pin directions, instead of pin values 35 // 0x1f000000 [28:24] : JMP_PIN (0): The GPIO number to use as condition for JMP PIN 36 // 0x00f80000 [23:19] : OUT_EN_SEL (0): Which data bit to use for inline OUT enable 37 // 0x00040000 [18] : INLINE_OUT_EN (0): If 1, use a bit of OUT data as an auxiliary write enable 38 // 0x00020000 [17] : OUT_STICKY (0): Continuously assert the most recent OUT/SET to the pins 39 // 0x0001f000 [16:12] : WRAP_TOP (0x1f): After reaching this address, execution is wrapped to wrap_bottom 40 // 0x00000f80 [11:7] : WRAP_BOTTOM (0): After reaching wrap_top, execution is wrapped to this address 41 // 0x00000010 [4] : STATUS_SEL (0): Comparison used for the MOV x, STATUS instruction 42 // 0x0000000f [3:0] : STATUS_N (0): Comparison level for the MOV x, STATUS instruction 43 io_rw_32 execctrl; 44 45 _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL 46 // Control behaviour of the input/output shift registers for state machine 0 47 // 0x80000000 [31] : FJOIN_RX (0): When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep 48 // 0x40000000 [30] : FJOIN_TX (0): When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep 49 // 0x3e000000 [29:25] : PULL_THRESH (0): Number of bits shifted out of OSR before autopull, or conditional pull (PULL... 50 // 0x01f00000 [24:20] : PUSH_THRESH (0): Number of bits shifted into ISR before autopush, or conditional push (PUSH... 51 // 0x00080000 [19] : OUT_SHIFTDIR (1): 1 = shift out of output shift register to right 52 // 0x00040000 [18] : IN_SHIFTDIR (1): 1 = shift input shift register to right (data enters from left) 53 // 0x00020000 [17] : AUTOPULL (0): Pull automatically when the output shift register is emptied, i 54 // 0x00010000 [16] : AUTOPUSH (0): Push automatically when the input shift register is filled, i 55 io_rw_32 shiftctrl; 56 57 _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR 58 // Current instruction address of state machine 0 59 // 0x0000001f [4:0] : SM0_ADDR (0) 60 io_ro_32 addr; 61 62 _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR 63 // Read to see the instruction currently addressed by state machine 0's program counter 64 // 0x0000ffff [15:0] : SM0_INSTR (0) 65 io_rw_32 instr; 66 67 _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL 68 // State machine pin control 69 // 0xe0000000 [31:29] : SIDESET_COUNT (0): The number of MSBs of the Delay/Side-set instruction field which are used... 70 // 0x1c000000 [28:26] : SET_COUNT (0x5): The number of pins asserted by a SET 71 // 0x03f00000 [25:20] : OUT_COUNT (0): The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction 72 // 0x000f8000 [19:15] : IN_BASE (0): The pin which is mapped to the least-significant bit of a state machine's IN data bus 73 // 0x00007c00 [14:10] : SIDESET_BASE (0): The lowest-numbered pin that will be affected by a side-set operation 74 // 0x000003e0 [9:5] : SET_BASE (0): The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction 75 // 0x0000001f [4:0] : OUT_BASE (0): The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV... 76 io_rw_32 pinctrl; 77 } pio_sm_hw_t; 78 79 typedef struct { 80 _REG_(PIO_CTRL_OFFSET) // PIO_CTRL 81 // PIO control register 82 // 0x00000f00 [11:8] : CLKDIV_RESTART (0): Restart a state machine's clock divider from an initial phase of 0 83 // 0x000000f0 [7:4] : SM_RESTART (0): Write 1 to instantly clear internal SM state which may be otherwise difficult... 84 // 0x0000000f [3:0] : SM_ENABLE (0): Enable/disable each of the four state machines by writing 1/0 to each of these four bits 85 io_rw_32 ctrl; 86 87 _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT 88 // FIFO status register 89 // 0x0f000000 [27:24] : TXEMPTY (0xf): State machine TX FIFO is empty 90 // 0x000f0000 [19:16] : TXFULL (0): State machine TX FIFO is full 91 // 0x00000f00 [11:8] : RXEMPTY (0xf): State machine RX FIFO is empty 92 // 0x0000000f [3:0] : RXFULL (0): State machine RX FIFO is full 93 io_ro_32 fstat; 94 95 _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG 96 // FIFO debug register 97 // 0x0f000000 [27:24] : TXSTALL (0): State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with... 98 // 0x000f0000 [19:16] : TXOVER (0): TX FIFO overflow (i 99 // 0x00000f00 [11:8] : RXUNDER (0): RX FIFO underflow (i 100 // 0x0000000f [3:0] : RXSTALL (0): State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with... 101 io_rw_32 fdebug; 102 103 _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL 104 // FIFO levels 105 // 0xf0000000 [31:28] : RX3 (0) 106 // 0x0f000000 [27:24] : TX3 (0) 107 // 0x00f00000 [23:20] : RX2 (0) 108 // 0x000f0000 [19:16] : TX2 (0) 109 // 0x0000f000 [15:12] : RX1 (0) 110 // 0x00000f00 [11:8] : TX1 (0) 111 // 0x000000f0 [7:4] : RX0 (0) 112 // 0x0000000f [3:0] : TX0 (0) 113 io_ro_32 flevel; 114 115 _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 116 // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes) 117 // 118 // Direct write access to the TX FIFO for this state machine 119 io_wo_32 txf[NUM_PIO_STATE_MACHINES]; // 4 120 121 _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 122 // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes) 123 // 124 // Direct read access to the RX FIFO for this state machine 125 io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; // 4 126 127 _REG_(PIO_IRQ_OFFSET) // PIO_IRQ 128 // State machine IRQ flags register 129 // 0x000000ff [7:0] : IRQ (0) 130 io_rw_32 irq; 131 132 _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE 133 // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ 134 // 0x000000ff [7:0] : IRQ_FORCE (0) 135 io_wo_32 irq_force; 136 137 _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS 138 // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities 139 io_rw_32 input_sync_bypass; 140 141 _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT 142 // Read to sample the pad output values PIO is currently driving to the GPIOs 143 io_ro_32 dbg_padout; 144 145 _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE 146 // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs 147 io_ro_32 dbg_padoe; 148 149 _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO 150 // The PIO hardware has some free parameters that may vary between chip products 151 // 0x003f0000 [21:16] : IMEM_SIZE (0): The size of the instruction memory, measured in units of one instruction 152 // 0x00000f00 [11:8] : SM_COUNT (0): The number of state machines this PIO instance is equipped with 153 // 0x0000003f [5:0] : FIFO_DEPTH (0): The depth of the state machine TX/RX FIFOs, measured in words 154 io_ro_32 dbg_cfginfo; 155 156 _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 157 // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes) 158 // 159 // Write-only access to instruction memory location 0 160 // 0x0000ffff [15:0] : INSTR_MEM0 (0) 161 io_wo_32 instr_mem[PIO_INSTRUCTION_COUNT]; // 32 162 163 pio_sm_hw_t sm[NUM_PIO_STATE_MACHINES]; // 4 164 165 _REG_(PIO_INTR_OFFSET) // PIO_INTR 166 // Raw Interrupts 167 // 0x00000800 [11] : SM3 (0) 168 // 0x00000400 [10] : SM2 (0) 169 // 0x00000200 [9] : SM1 (0) 170 // 0x00000100 [8] : SM0 (0) 171 // 0x00000080 [7] : SM3_TXNFULL (0) 172 // 0x00000040 [6] : SM2_TXNFULL (0) 173 // 0x00000020 [5] : SM1_TXNFULL (0) 174 // 0x00000010 [4] : SM0_TXNFULL (0) 175 // 0x00000008 [3] : SM3_RXNEMPTY (0) 176 // 0x00000004 [2] : SM2_RXNEMPTY (0) 177 // 0x00000002 [1] : SM1_RXNEMPTY (0) 178 // 0x00000001 [0] : SM0_RXNEMPTY (0) 179 io_ro_32 intr; 180 181 _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE 182 // Interrupt Enable for irq0 183 // 0x00000800 [11] : SM3 (0) 184 // 0x00000400 [10] : SM2 (0) 185 // 0x00000200 [9] : SM1 (0) 186 // 0x00000100 [8] : SM0 (0) 187 // 0x00000080 [7] : SM3_TXNFULL (0) 188 // 0x00000040 [6] : SM2_TXNFULL (0) 189 // 0x00000020 [5] : SM1_TXNFULL (0) 190 // 0x00000010 [4] : SM0_TXNFULL (0) 191 // 0x00000008 [3] : SM3_RXNEMPTY (0) 192 // 0x00000004 [2] : SM2_RXNEMPTY (0) 193 // 0x00000002 [1] : SM1_RXNEMPTY (0) 194 // 0x00000001 [0] : SM0_RXNEMPTY (0) 195 io_rw_32 inte0; 196 197 _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF 198 // Interrupt Force for irq0 199 // 0x00000800 [11] : SM3 (0) 200 // 0x00000400 [10] : SM2 (0) 201 // 0x00000200 [9] : SM1 (0) 202 // 0x00000100 [8] : SM0 (0) 203 // 0x00000080 [7] : SM3_TXNFULL (0) 204 // 0x00000040 [6] : SM2_TXNFULL (0) 205 // 0x00000020 [5] : SM1_TXNFULL (0) 206 // 0x00000010 [4] : SM0_TXNFULL (0) 207 // 0x00000008 [3] : SM3_RXNEMPTY (0) 208 // 0x00000004 [2] : SM2_RXNEMPTY (0) 209 // 0x00000002 [1] : SM1_RXNEMPTY (0) 210 // 0x00000001 [0] : SM0_RXNEMPTY (0) 211 io_rw_32 intf0; 212 213 _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS 214 // Interrupt status after masking & forcing for irq0 215 // 0x00000800 [11] : SM3 (0) 216 // 0x00000400 [10] : SM2 (0) 217 // 0x00000200 [9] : SM1 (0) 218 // 0x00000100 [8] : SM0 (0) 219 // 0x00000080 [7] : SM3_TXNFULL (0) 220 // 0x00000040 [6] : SM2_TXNFULL (0) 221 // 0x00000020 [5] : SM1_TXNFULL (0) 222 // 0x00000010 [4] : SM0_TXNFULL (0) 223 // 0x00000008 [3] : SM3_RXNEMPTY (0) 224 // 0x00000004 [2] : SM2_RXNEMPTY (0) 225 // 0x00000002 [1] : SM1_RXNEMPTY (0) 226 // 0x00000001 [0] : SM0_RXNEMPTY (0) 227 io_ro_32 ints0; 228 229 _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE 230 // Interrupt Enable for irq1 231 // 0x00000800 [11] : SM3 (0) 232 // 0x00000400 [10] : SM2 (0) 233 // 0x00000200 [9] : SM1 (0) 234 // 0x00000100 [8] : SM0 (0) 235 // 0x00000080 [7] : SM3_TXNFULL (0) 236 // 0x00000040 [6] : SM2_TXNFULL (0) 237 // 0x00000020 [5] : SM1_TXNFULL (0) 238 // 0x00000010 [4] : SM0_TXNFULL (0) 239 // 0x00000008 [3] : SM3_RXNEMPTY (0) 240 // 0x00000004 [2] : SM2_RXNEMPTY (0) 241 // 0x00000002 [1] : SM1_RXNEMPTY (0) 242 // 0x00000001 [0] : SM0_RXNEMPTY (0) 243 io_rw_32 inte1; 244 245 _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF 246 // Interrupt Force for irq1 247 // 0x00000800 [11] : SM3 (0) 248 // 0x00000400 [10] : SM2 (0) 249 // 0x00000200 [9] : SM1 (0) 250 // 0x00000100 [8] : SM0 (0) 251 // 0x00000080 [7] : SM3_TXNFULL (0) 252 // 0x00000040 [6] : SM2_TXNFULL (0) 253 // 0x00000020 [5] : SM1_TXNFULL (0) 254 // 0x00000010 [4] : SM0_TXNFULL (0) 255 // 0x00000008 [3] : SM3_RXNEMPTY (0) 256 // 0x00000004 [2] : SM2_RXNEMPTY (0) 257 // 0x00000002 [1] : SM1_RXNEMPTY (0) 258 // 0x00000001 [0] : SM0_RXNEMPTY (0) 259 io_rw_32 intf1; 260 261 _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS 262 // Interrupt status after masking & forcing for irq1 263 // 0x00000800 [11] : SM3 (0) 264 // 0x00000400 [10] : SM2 (0) 265 // 0x00000200 [9] : SM1 (0) 266 // 0x00000100 [8] : SM0 (0) 267 // 0x00000080 [7] : SM3_TXNFULL (0) 268 // 0x00000040 [6] : SM2_TXNFULL (0) 269 // 0x00000020 [5] : SM1_TXNFULL (0) 270 // 0x00000010 [4] : SM0_TXNFULL (0) 271 // 0x00000008 [3] : SM3_RXNEMPTY (0) 272 // 0x00000004 [2] : SM2_RXNEMPTY (0) 273 // 0x00000002 [1] : SM1_RXNEMPTY (0) 274 // 0x00000001 [0] : SM0_RXNEMPTY (0) 275 io_ro_32 ints1; 276 } pio_hw_t; 277 278 #define pio0_hw ((pio_hw_t *)PIO0_BASE) 279 #define pio1_hw ((pio_hw_t *)PIO1_BASE) 280 281 static_assert( NUM_PIO_STATE_MACHINES == 4, ""); 282 static_assert( PIO_INSTRUCTION_COUNT == 32, ""); 283 284 #endif 285