1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /* 4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _HARDWARE_STRUCTS_PLL_H 10 #define _HARDWARE_STRUCTS_PLL_H 11 12 #include "hardware/address_mapped.h" 13 #include "hardware/regs/pll.h" 14 15 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll 16 // 17 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 18 // _REG_(x) will link to the corresponding register in hardware/regs/pll.h. 19 // 20 // Bit-field descriptions are of the form: 21 // BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION 22 23 /// \tag::pll_hw[] 24 typedef struct { 25 _REG_(PLL_CS_OFFSET) // PLL_CS 26 // Control and Status 27 // 0x80000000 [31] : LOCK (0): PLL is locked 28 // 0x00000100 [8] : BYPASS (0): Passes the reference clock to the output instead of the divided VCO 29 // 0x0000003f [5:0] : REFDIV (1): Divides the PLL input reference clock 30 io_rw_32 cs; 31 32 _REG_(PLL_PWR_OFFSET) // PLL_PWR 33 // Controls the PLL power modes 34 // 0x00000020 [5] : VCOPD (1): PLL VCO powerdown 35 // 0x00000008 [3] : POSTDIVPD (1): PLL post divider powerdown 36 // 0x00000004 [2] : DSMPD (1): PLL DSM powerdown 37 // 0x00000001 [0] : PD (1): PLL powerdown 38 io_rw_32 pwr; 39 40 _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT 41 // Feedback divisor 42 // 0x00000fff [11:0] : FBDIV_INT (0): see ctrl reg description for constraints 43 io_rw_32 fbdiv_int; 44 45 _REG_(PLL_PRIM_OFFSET) // PLL_PRIM 46 // Controls the PLL post dividers for the primary output 47 // 0x00070000 [18:16] : POSTDIV1 (0x7): divide by 1-7 48 // 0x00007000 [14:12] : POSTDIV2 (0x7): divide by 1-7 49 io_rw_32 prim; 50 } pll_hw_t; 51 52 #define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE) 53 #define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE) 54 /// \end::pll_hw[] 55 56 #endif 57