1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /* 4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _HARDWARE_STRUCTS_SCB_H 10 #define _HARDWARE_STRUCTS_SCB_H 11 12 #include "hardware/address_mapped.h" 13 #include "hardware/regs/m0plus.h" 14 15 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus 16 // 17 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 18 // _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. 19 // 20 // Bit-field descriptions are of the form: 21 // BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION 22 23 typedef struct { 24 _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID 25 // Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor... 26 // 0xff000000 [31:24] : IMPLEMENTER (0x41): Implementor code: 0x41 = ARM 27 // 0x00f00000 [23:20] : VARIANT (0): Major revision number n in the rnpm revision status: 28 // 0x000f0000 [19:16] : ARCHITECTURE (0xc): Constant that defines the architecture of the processor: 29 // 0x0000fff0 [15:4] : PARTNO (0xc60): Number of processor within family: 0xC60 = Cortex-M0+ 30 // 0x0000000f [3:0] : REVISION (1): Minor revision number m in the rnpm revision status: 31 io_ro_32 cpuid; 32 33 _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR 34 // Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending... 35 // 0x80000000 [31] : NMIPENDSET (0): Setting this bit will activate an NMI 36 // 0x10000000 [28] : PENDSVSET (0): PendSV set-pending bit 37 // 0x08000000 [27] : PENDSVCLR (0): PendSV clear-pending bit 38 // 0x04000000 [26] : PENDSTSET (0): SysTick exception set-pending bit 39 // 0x02000000 [25] : PENDSTCLR (0): SysTick exception clear-pending bit 40 // 0x00800000 [23] : ISRPREEMPT (0): The system can only access this bit when the core is halted 41 // 0x00400000 [22] : ISRPENDING (0): External interrupt pending flag 42 // 0x001ff000 [20:12] : VECTPENDING (0): Indicates the exception number for the highest priority pending exception: 0 =... 43 // 0x000001ff [8:0] : VECTACTIVE (0): Active exception number field 44 io_rw_32 icsr; 45 46 _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR 47 // The VTOR holds the vector table offset address 48 // 0xffffff00 [31:8] : TBLOFF (0): Bits [31:8] of the indicate the vector table offset address 49 io_rw_32 vtor; 50 51 _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR 52 // Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state... 53 // 0xffff0000 [31:16] : VECTKEY (0): Register key: 54 // 0x00008000 [15] : ENDIANESS (0): Data endianness implemented: 55 // 0x00000004 [2] : SYSRESETREQ (0): Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be... 56 // 0x00000002 [1] : VECTCLRACTIVE (0): Clears all active state information for fixed and configurable exceptions 57 io_rw_32 aircr; 58 59 _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR 60 // System Control Register 61 // 0x00000010 [4] : SEVONPEND (0): Send Event on Pending bit: 62 // 0x00000004 [2] : SLEEPDEEP (0): Controls whether the processor uses sleep or deep sleep as its low power mode: 63 // 0x00000002 [1] : SLEEPONEXIT (0): Indicates sleep-on-exit when returning from Handler mode to Thread mode: 64 io_rw_32 scr; 65 } armv6m_scb_t; 66 67 #define scb_hw ((armv6m_scb_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET)) 68 69 #endif 70