1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /* 4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _HARDWARE_STRUCTS_UART_H 10 #define _HARDWARE_STRUCTS_UART_H 11 12 #include "hardware/address_mapped.h" 13 #include "hardware/regs/uart.h" 14 15 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart 16 // 17 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 18 // _REG_(x) will link to the corresponding register in hardware/regs/uart.h. 19 // 20 // Bit-field descriptions are of the form: 21 // BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION 22 23 typedef struct { 24 _REG_(UART_UARTDR_OFFSET) // UART_UARTDR 25 // Data Register, UARTDR 26 // 0x00000800 [11] : OE (0): Overrun error 27 // 0x00000400 [10] : BE (0): Break error 28 // 0x00000200 [9] : PE (0): Parity error 29 // 0x00000100 [8] : FE (0): Framing error 30 // 0x000000ff [7:0] : DATA (0): Receive (read) data character 31 io_rw_32 dr; 32 33 _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR 34 // Receive Status Register/Error Clear Register, UARTRSR/UARTECR 35 // 0x00000008 [3] : OE (0): Overrun error 36 // 0x00000004 [2] : BE (0): Break error 37 // 0x00000002 [1] : PE (0): Parity error 38 // 0x00000001 [0] : FE (0): Framing error 39 io_rw_32 rsr; 40 41 uint32_t _pad0[4]; 42 43 _REG_(UART_UARTFR_OFFSET) // UART_UARTFR 44 // Flag Register, UARTFR 45 // 0x00000100 [8] : RI (0): Ring indicator 46 // 0x00000080 [7] : TXFE (1): Transmit FIFO empty 47 // 0x00000040 [6] : RXFF (0): Receive FIFO full 48 // 0x00000020 [5] : TXFF (0): Transmit FIFO full 49 // 0x00000010 [4] : RXFE (1): Receive FIFO empty 50 // 0x00000008 [3] : BUSY (0): UART busy 51 // 0x00000004 [2] : DCD (0): Data carrier detect 52 // 0x00000002 [1] : DSR (0): Data set ready 53 // 0x00000001 [0] : CTS (0): Clear to send 54 io_ro_32 fr; 55 56 uint32_t _pad1; 57 58 _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR 59 // IrDA Low-Power Counter Register, UARTILPR 60 // 0x000000ff [7:0] : ILPDVSR (0): 8-bit low-power divisor value 61 io_rw_32 ilpr; 62 63 _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD 64 // Integer Baud Rate Register, UARTIBRD 65 // 0x0000ffff [15:0] : BAUD_DIVINT (0): The integer baud rate divisor 66 io_rw_32 ibrd; 67 68 _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD 69 // Fractional Baud Rate Register, UARTFBRD 70 // 0x0000003f [5:0] : BAUD_DIVFRAC (0): The fractional baud rate divisor 71 io_rw_32 fbrd; 72 73 _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H 74 // Line Control Register, UARTLCR_H 75 // 0x00000080 [7] : SPS (0): Stick parity select 76 // 0x00000060 [6:5] : WLEN (0): Word length 77 // 0x00000010 [4] : FEN (0): Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become... 78 // 0x00000008 [3] : STP2 (0): Two stop bits select 79 // 0x00000004 [2] : EPS (0): Even parity select 80 // 0x00000002 [1] : PEN (0): Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 =... 81 // 0x00000001 [0] : BRK (0): Send break 82 io_rw_32 lcr_h; 83 84 _REG_(UART_UARTCR_OFFSET) // UART_UARTCR 85 // Control Register, UARTCR 86 // 0x00008000 [15] : CTSEN (0): CTS hardware flow control enable 87 // 0x00004000 [14] : RTSEN (0): RTS hardware flow control enable 88 // 0x00002000 [13] : OUT2 (0): This bit is the complement of the UART Out2 (nUARTOut2) modem status output 89 // 0x00001000 [12] : OUT1 (0): This bit is the complement of the UART Out1 (nUARTOut1) modem status output 90 // 0x00000800 [11] : RTS (0): Request to send 91 // 0x00000400 [10] : DTR (0): Data transmit ready 92 // 0x00000200 [9] : RXE (1): Receive enable 93 // 0x00000100 [8] : TXE (1): Transmit enable 94 // 0x00000080 [7] : LBE (0): Loopback enable 95 // 0x00000004 [2] : SIRLP (0): SIR low-power IrDA mode 96 // 0x00000002 [1] : SIREN (0): SIR enable: 0 = IrDA SIR ENDEC is disabled 97 // 0x00000001 [0] : UARTEN (0): UART enable: 0 = UART is disabled 98 io_rw_32 cr; 99 100 _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS 101 // Interrupt FIFO Level Select Register, UARTIFLS 102 // 0x00000038 [5:3] : RXIFLSEL (0x2): Receive interrupt FIFO level select 103 // 0x00000007 [2:0] : TXIFLSEL (0x2): Transmit interrupt FIFO level select 104 io_rw_32 ifls; 105 106 _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC 107 // Interrupt Mask Set/Clear Register, UARTIMSC 108 // 0x00000400 [10] : OEIM (0): Overrun error interrupt mask 109 // 0x00000200 [9] : BEIM (0): Break error interrupt mask 110 // 0x00000100 [8] : PEIM (0): Parity error interrupt mask 111 // 0x00000080 [7] : FEIM (0): Framing error interrupt mask 112 // 0x00000040 [6] : RTIM (0): Receive timeout interrupt mask 113 // 0x00000020 [5] : TXIM (0): Transmit interrupt mask 114 // 0x00000010 [4] : RXIM (0): Receive interrupt mask 115 // 0x00000008 [3] : DSRMIM (0): nUARTDSR modem interrupt mask 116 // 0x00000004 [2] : DCDMIM (0): nUARTDCD modem interrupt mask 117 // 0x00000002 [1] : CTSMIM (0): nUARTCTS modem interrupt mask 118 // 0x00000001 [0] : RIMIM (0): nUARTRI modem interrupt mask 119 io_rw_32 imsc; 120 121 _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS 122 // Raw Interrupt Status Register, UARTRIS 123 // 0x00000400 [10] : OERIS (0): Overrun error interrupt status 124 // 0x00000200 [9] : BERIS (0): Break error interrupt status 125 // 0x00000100 [8] : PERIS (0): Parity error interrupt status 126 // 0x00000080 [7] : FERIS (0): Framing error interrupt status 127 // 0x00000040 [6] : RTRIS (0): Receive timeout interrupt status 128 // 0x00000020 [5] : TXRIS (0): Transmit interrupt status 129 // 0x00000010 [4] : RXRIS (0): Receive interrupt status 130 // 0x00000008 [3] : DSRRMIS (0): nUARTDSR modem interrupt status 131 // 0x00000004 [2] : DCDRMIS (0): nUARTDCD modem interrupt status 132 // 0x00000002 [1] : CTSRMIS (0): nUARTCTS modem interrupt status 133 // 0x00000001 [0] : RIRMIS (0): nUARTRI modem interrupt status 134 io_ro_32 ris; 135 136 _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS 137 // Masked Interrupt Status Register, UARTMIS 138 // 0x00000400 [10] : OEMIS (0): Overrun error masked interrupt status 139 // 0x00000200 [9] : BEMIS (0): Break error masked interrupt status 140 // 0x00000100 [8] : PEMIS (0): Parity error masked interrupt status 141 // 0x00000080 [7] : FEMIS (0): Framing error masked interrupt status 142 // 0x00000040 [6] : RTMIS (0): Receive timeout masked interrupt status 143 // 0x00000020 [5] : TXMIS (0): Transmit masked interrupt status 144 // 0x00000010 [4] : RXMIS (0): Receive masked interrupt status 145 // 0x00000008 [3] : DSRMMIS (0): nUARTDSR modem masked interrupt status 146 // 0x00000004 [2] : DCDMMIS (0): nUARTDCD modem masked interrupt status 147 // 0x00000002 [1] : CTSMMIS (0): nUARTCTS modem masked interrupt status 148 // 0x00000001 [0] : RIMMIS (0): nUARTRI modem masked interrupt status 149 io_ro_32 mis; 150 151 _REG_(UART_UARTICR_OFFSET) // UART_UARTICR 152 // Interrupt Clear Register, UARTICR 153 // 0x00000400 [10] : OEIC (0): Overrun error interrupt clear 154 // 0x00000200 [9] : BEIC (0): Break error interrupt clear 155 // 0x00000100 [8] : PEIC (0): Parity error interrupt clear 156 // 0x00000080 [7] : FEIC (0): Framing error interrupt clear 157 // 0x00000040 [6] : RTIC (0): Receive timeout interrupt clear 158 // 0x00000020 [5] : TXIC (0): Transmit interrupt clear 159 // 0x00000010 [4] : RXIC (0): Receive interrupt clear 160 // 0x00000008 [3] : DSRMIC (0): nUARTDSR modem interrupt clear 161 // 0x00000004 [2] : DCDMIC (0): nUARTDCD modem interrupt clear 162 // 0x00000002 [1] : CTSMIC (0): nUARTCTS modem interrupt clear 163 // 0x00000001 [0] : RIMIC (0): nUARTRI modem interrupt clear 164 io_rw_32 icr; 165 166 _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR 167 // DMA Control Register, UARTDMACR 168 // 0x00000004 [2] : DMAONERR (0): DMA on error 169 // 0x00000002 [1] : TXDMAE (0): Transmit DMA enable 170 // 0x00000001 [0] : RXDMAE (0): Receive DMA enable 171 io_rw_32 dmacr; 172 } uart_hw_t; 173 174 #define uart0_hw ((uart_hw_t *)UART0_BASE) 175 #define uart1_hw ((uart_hw_t *)UART1_BASE) 176 177 #endif 178