1 /*
2 * Copyright (c) 2009 Corey Tabaka
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8 #include <sys/types.h>
9 #include <lk/err.h>
10 #include <lk/reg.h>
11 #include <lk/debug.h>
12 #include <lk/trace.h>
13 #include <assert.h>
14 #include <kernel/thread.h>
15 #include <kernel/spinlock.h>
16 #include <platform.h>
17 #include <platform/interrupts.h>
18 #include <platform/console.h>
19 #include <platform/timer.h>
20 #include <platform/pc.h>
21 #include <platform/pc/timer.h>
22 #include "platform_p.h"
23 #include <arch/x86.h>
24 #include <inttypes.h>
25
26 #define LOCAL_TRACE 0
27
28 // TODO: switch this logic to lib/fixed_point math
29
30 static platform_timer_callback t_callback;
31 static void *callback_arg;
32 static spin_lock_t lock = SPIN_LOCK_INITIAL_VALUE;
33
34 static uint64_t ticks_per_ms;
35
36 // next callback event time in 32.32 fixed point milliseconds
37 static uint64_t next_trigger_time;
38
39 // if periodic, the delta to set to the next event. if oneshot, 0
40 static uint64_t next_trigger_delta;
41
42 // time in 32.32 fixed point milliseconds
43 static volatile uint64_t timer_current_time;
44 // delta time per periodic tick in 32.32
45 static uint64_t timer_delta_time;
46
47 #define INTERNAL_FREQ 1193182ULL
48 #define INTERNAL_FREQ_3X 3579546ULL
49 #define INTERNAL_FREQ_TICKS_PER_MS (INTERNAL_FREQ / 1000u)
50
51 /* Maximum amount of time that can be program on the timer to schedule the next
52 * interrupt, in milliseconds */
53 #define MAX_TIMER_INTERVAL 55
54
pit_current_time(void)55 lk_time_t pit_current_time(void) {
56 spin_lock_saved_state_t state;
57 spin_lock_irqsave(&lock, state);
58
59 lk_time_t time = (lk_time_t) (timer_current_time >> 32);
60
61 spin_unlock_irqrestore(&lock, state);
62
63 return time;
64 }
65
pit_current_time_hires(void)66 lk_bigtime_t pit_current_time_hires(void) {
67 spin_lock_saved_state_t state;
68 spin_lock_irqsave(&lock, state);
69
70 lk_bigtime_t time = (lk_bigtime_t) ((timer_current_time >> 22) * 1000) >> 10;
71
72 spin_unlock_irqrestore(&lock, state);
73
74 return time;
75 }
76
pit_timer_tick(void * arg)77 static enum handler_return pit_timer_tick(void *arg) {
78 if (next_trigger_time != 0 || next_trigger_delta) {
79 LTRACEF("ntt %#" PRIx64 ", ntd %#" PRIx64 "\n", next_trigger_time, next_trigger_delta);
80 }
81
82 spin_lock(&lock);
83 timer_current_time += timer_delta_time;
84 spin_unlock(&lock);
85
86 lk_time_t time = current_time();
87
88 if (t_callback && next_trigger_time != 0 && timer_current_time >= next_trigger_time) {
89 if (next_trigger_delta != 0) {
90 uint64_t delta = timer_current_time - next_trigger_time;
91 next_trigger_time = timer_current_time + next_trigger_delta - delta;
92 } else {
93 next_trigger_time = 0;
94 }
95
96 return t_callback(callback_arg, time);
97 } else {
98 return INT_NO_RESCHEDULE;
99 }
100 }
101
set_pit_frequency(uint32_t frequency)102 static void set_pit_frequency(uint32_t frequency) {
103 uint32_t count, remainder;
104
105 LTRACEF("frequency %u\n", frequency);
106
107 /* figure out the correct divisor for the desired frequency */
108 if (frequency <= 18) {
109 count = 0xffff;
110 } else if (frequency >= INTERNAL_FREQ) {
111 count = 1;
112 } else {
113 count = INTERNAL_FREQ_3X / frequency;
114 remainder = INTERNAL_FREQ_3X % frequency;
115
116 if (remainder >= INTERNAL_FREQ_3X / 2) {
117 count += 1;
118 }
119
120 count /= 3;
121 remainder = count % 3;
122
123 if (remainder >= 1) {
124 count += 1;
125 }
126 }
127
128 uint16_t divisor = count & 0xffff;
129
130 /*
131 * funky math that i don't feel like explaining. essentially 32.32 fixed
132 * point representation of the configured timer delta.
133 */
134 timer_delta_time = (3685982306ULL * count) >> 10;
135
136 LTRACEF("dt %#x.%08x\n", (uint32_t)(timer_delta_time >> 32), (uint32_t)(timer_delta_time & 0xffffffff));
137 LTRACEF("divisor %" PRIu16 "\n", divisor);
138
139 /*
140 * setup the Programmable Interval Timer
141 * timer 0, mode 2, binary counter, LSB followed by MSB
142 */
143 outp(I8253_CONTROL_REG, 0x34);
144 outp(I8253_DATA_REG, divisor & 0xff); // LSB
145 outp(I8253_DATA_REG, divisor >> 8); // MSB
146 }
147
pit_init(void)148 void pit_init(void) {
149 // start the PIT at 1Khz in free-running mode to keep a time base
150 timer_current_time = 0;
151 ticks_per_ms = INTERNAL_FREQ/1000;
152 set_pit_frequency(1000); // ~1ms granularity
153 register_int_handler(INT_PIT, &pit_timer_tick, NULL);
154 unmask_interrupt(INT_PIT);
155 }
156
pit_set_periodic_timer(platform_timer_callback callback,void * arg,lk_time_t interval)157 status_t pit_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval) {
158 LTRACEF("pit_set_periodic_timer: interval %u\n", interval);
159
160 spin_lock_saved_state_t state;
161 spin_lock_irqsave(&lock, state);
162
163 t_callback = callback;
164 callback_arg = arg;
165
166 next_trigger_delta = (uint64_t) interval << 32;
167 next_trigger_time = timer_current_time + next_trigger_delta;
168
169 unmask_interrupt(INT_PIT);
170 spin_unlock_irqrestore(&lock, state);
171
172 return NO_ERROR;
173 }
174
pit_set_oneshot_timer(platform_timer_callback callback,void * arg,lk_time_t interval)175 status_t pit_set_oneshot_timer(platform_timer_callback callback, void *arg, lk_time_t interval) {
176 LTRACEF("pit_set_oneshot_timer: interval %u\n", interval);
177
178 spin_lock_saved_state_t state;
179 spin_lock_irqsave(&lock, state);
180
181 t_callback = callback;
182 callback_arg = arg;
183
184 next_trigger_delta = 0;
185 next_trigger_time = timer_current_time + ((uint64_t)interval << 32);
186
187 unmask_interrupt(INT_PIT);
188 spin_unlock_irqrestore(&lock, state);
189
190 return NO_ERROR;
191 }
192
pit_cancel_timer(void)193 void pit_cancel_timer(void) {
194 LTRACE;
195
196 spin_lock_saved_state_t state;
197 spin_lock_irqsave(&lock, state);
198
199 next_trigger_time = 0;
200
201 spin_unlock_irqrestore(&lock, state);
202 }
203
pit_stop_timer(void)204 void pit_stop_timer(void) {
205 LTRACE;
206
207 spin_lock_saved_state_t state;
208 spin_lock_irqsave(&lock, state);
209
210 next_trigger_time = 0;
211 next_trigger_delta = 0;
212
213 // stop the PIT
214 outp(I8253_CONTROL_REG, 0x34);
215 outp(I8253_DATA_REG, 0); // LSB
216 outp(I8253_DATA_REG, 0); // MSB
217 mask_interrupt(INT_PIT);
218
219 spin_unlock_irqrestore(&lock, state);
220 }
221
pit_calibrate_tsc(void)222 uint64_t pit_calibrate_tsc(void) {
223 DEBUG_ASSERT(arch_ints_disabled());
224
225 uint64_t tsc_ticks[5] = {0};
226 uint32_t countdown_ms[5] = {0};
227
228 uint64_t tsc_freq = 0;
229 for (uint i = 0; i < countof(tsc_ticks); i++) {
230 // calibrate the tsc frequency using the PIT
231 countdown_ms[i] = 2 * (i + 1);
232
233 uint16_t pic_ticks = INTERNAL_FREQ_TICKS_PER_MS * countdown_ms[i];
234 outp(I8253_CONTROL_REG, 0x30);
235 outp(I8253_DATA_REG, pic_ticks & 0xff); // LSB
236 outp(I8253_DATA_REG, pic_ticks >> 8); // MSB
237
238 // read the tsc
239 uint64_t tsc_start = __builtin_ia32_rdtsc();
240
241 // wait for countdown_ms
242 uint8_t status = 0;
243 do {
244 // Send a read-back command that latches the status of ch0
245 outp(I8253_CONTROL_REG, 0xe2);
246 status = inp(I8253_DATA_REG);
247 // Wait for bit 7 (output) to go high and for bit 6 (null count) to go low
248 } while ((status & 0xc0) != 0x80);
249
250 uint64_t tsc_end = __builtin_ia32_rdtsc();
251 tsc_ticks[i] = tsc_end - tsc_start;
252 }
253
254 // find the best time
255 uint best_index = 0;
256 for (uint i = 1; i < countof(tsc_ticks); i++) {
257 if (tsc_ticks[i] < tsc_ticks[best_index]) {
258 best_index = i;
259 }
260 }
261
262 // calculate the tsc frequency
263 tsc_freq = (tsc_ticks[best_index] * 1000) / countdown_ms[best_index];
264 dprintf(INFO, "PIT: calibrated TSC frequency: %" PRIu64 "Hz\n", tsc_freq);
265
266 // put the PIT back to 1ms countdown
267 set_pit_frequency(1000);
268
269 return tsc_freq;
270 }
271
pit_calibrate_lapic(uint32_t (* lapic_read_tick)(void))272 uint32_t pit_calibrate_lapic(uint32_t (*lapic_read_tick)(void)) {
273 DEBUG_ASSERT(arch_ints_disabled());
274
275 uint64_t lapic_ticks[5] = {0};
276 uint32_t countdown_ms[5] = {0};
277
278 for (uint i = 0; i < countof(lapic_ticks); i++) {
279 // calibrate the tsc frequency using the PIT
280 countdown_ms[i] = 2 * (i + 1);
281
282 uint16_t pic_ticks = INTERNAL_FREQ_TICKS_PER_MS * countdown_ms[i];
283 outp(I8253_CONTROL_REG, 0x30);
284 outp(I8253_DATA_REG, pic_ticks & 0xff); // LSB
285 outp(I8253_DATA_REG, pic_ticks >> 8); // MSB
286
287 // read the tsc
288 uint32_t tick_start = lapic_read_tick();
289
290 // wait for countdown_ms
291 uint8_t status = 0;
292 do {
293 // Send a read-back command that latches the status of ch0
294 outp(I8253_CONTROL_REG, 0xe2);
295 status = inp(I8253_DATA_REG);
296 // Wait for bit 7 (output) to go high and for bit 6 (null count) to go low
297 } while ((status & 0xc0) != 0x80);
298
299 uint32_t tick_end = lapic_read_tick();
300 lapic_ticks[i] = tick_start - tick_end;
301 }
302
303 // find the best time
304 uint best_index = 0;
305 for (uint i = 1; i < countof(lapic_ticks); i++) {
306 if (lapic_ticks[i] < lapic_ticks[best_index]) {
307 best_index = i;
308 }
309 }
310
311 // calculate the tsc frequency
312 uint32_t freq = (lapic_ticks[best_index] * 1000) / countdown_ms[best_index];
313 dprintf(INFO, "PIT: calibrated local apic frequency: %" PRIu32 "Hz\n", freq);
314
315 // put the PIT back to 1ms countdown
316 set_pit_frequency(1000);
317
318 return freq;
319 }