Lines Matching refs:dmc
27 static int dmc500_config(struct mod_dmc500_reg *dmc, fwk_id_t ddr_phy_id);
76 struct mod_dmc500_reg *dmc; in mod_dmc500_start() local
83 dmc = (struct mod_dmc500_reg *)element_config->dmc; in mod_dmc500_start()
85 return dmc500_config(dmc, element_config->ddr_phy_id); in mod_dmc500_start()
99 static int dmc500_config(struct mod_dmc500_reg *dmc, fwk_id_t ddr_phy_id) in dmc500_config() argument
111 FWK_LOG_INFO("[DDR] Initialising DMC500 at 0x%x", (uintptr_t)dmc); in dmc500_config()
113 dmc->ADDRESS_CONTROL = reg_val->ADDRESS_CONTROL; in dmc500_config()
114 dmc->RANK_REMAP_CONTROL = reg_val->RANK_REMAP_CONTROL; in dmc500_config()
115 dmc->MEMORY_TYPE = reg_val->MEMORY_TYPE; in dmc500_config()
116 dmc->FORMAT_CONTROL = reg_val->FORMAT_CONTROL; in dmc500_config()
117 dmc->DECODE_CONTROL = reg_val->DECODE_CONTROL; in dmc500_config()
118 dmc->FEATURE_CONTROL = reg_val->FEATURE_CONTROL; in dmc500_config()
119 dmc->ODT_WR_CONTROL_31_00 = reg_val->ODT_WR_CONTROL_31_00; in dmc500_config()
120 dmc->ODT_RD_CONTROL_31_00 = reg_val->ODT_RD_CONTROL_31_00; in dmc500_config()
121 dmc->ODT_TIMING = reg_val->ODT_TIMING; in dmc500_config()
125 dmc->T_REFI = reg_val->T_REFI; in dmc500_config()
126 dmc->T_RFC = reg_val->T_RFC; in dmc500_config()
127 dmc->T_RDPDEN = reg_val->T_RDPDEN; in dmc500_config()
128 dmc->T_RCD = reg_val->T_RCD; in dmc500_config()
129 dmc->T_RAS = reg_val->T_RAS; in dmc500_config()
130 dmc->T_RP = reg_val->T_RP; in dmc500_config()
131 dmc->T_RRD = reg_val->T_RRD; in dmc500_config()
132 dmc->T_ACT_WINDOW = reg_val->T_ACT_WINDOW; in dmc500_config()
133 dmc->T_RTR = reg_val->T_RTR; in dmc500_config()
134 dmc->T_RTW = reg_val->T_RTW; in dmc500_config()
135 dmc->T_RTP = reg_val->T_RTP; in dmc500_config()
136 dmc->T_WR = reg_val->T_WR; in dmc500_config()
137 dmc->T_WTR = reg_val->T_WTR; in dmc500_config()
138 dmc->T_WTW = reg_val->T_WTW; in dmc500_config()
139 dmc->T_XTMW = reg_val->T_XTMW; in dmc500_config()
140 dmc->T_CLOCK_CONTROL = reg_val->T_CLOCK_CONTROL; in dmc500_config()
141 dmc->T_EP = reg_val->T_EP; in dmc500_config()
142 dmc->T_XP = reg_val->T_XP; in dmc500_config()
143 dmc->T_ESR = reg_val->T_ESR; in dmc500_config()
144 dmc->T_XSR = reg_val->T_XSR; in dmc500_config()
148 dmc->ADDRESS_MAP = reg_val->ADDRESS_MAP; in dmc500_config()
152 dmc->SI0_SI_INTERRUPT_CONTROL = reg_val->SI0_SI_INTERRUPT_CONTROL; in dmc500_config()
153 dmc->SI0_PMU_REQ_CONTROL = reg_val->SI0_PMU_REQ_CONTROL; in dmc500_config()
154 dmc->SI0_PMU_REQ_ATTRIBUTE_MASK_0 = reg_val->SI0_PMU_REQ_ATTRIBUTE_MASK_0; in dmc500_config()
155 dmc->SI0_PMU_REQ_ATTRIBUTE_MATCH_0 = reg_val->SI0_PMU_REQ_ATTRIBUTE_MATCH_0; in dmc500_config()
156 dmc->SI0_PMU_REQ_ATTRIBUTE_MASK_1 = reg_val->SI0_PMU_REQ_ATTRIBUTE_MASK_1; in dmc500_config()
157 dmc->SI0_PMU_REQ_ATTRIBUTE_MATCH_1 = reg_val->SI0_PMU_REQ_ATTRIBUTE_MATCH_1; in dmc500_config()
158 dmc->SI0_PMU_REQ_ATTRIBUTE_MASK_2 = reg_val->SI0_PMU_REQ_ATTRIBUTE_MASK_2; in dmc500_config()
159 dmc->SI0_PMU_REQ_ATTRIBUTE_MATCH_2 = reg_val->SI0_PMU_REQ_ATTRIBUTE_MATCH_2; in dmc500_config()
160 dmc->SI0_PMU_REQ_ATTRIBUTE_MASK_3 = reg_val->SI0_PMU_REQ_ATTRIBUTE_MASK_3; in dmc500_config()
161 dmc->SI0_PMU_REQ_ATTRIBUTE_MATCH_3 = reg_val->SI0_PMU_REQ_ATTRIBUTE_MATCH_3; in dmc500_config()
162 dmc->SI0_THRESHOLD_CONTROL = reg_val->SI0_THRESHOLD_CONTROL; in dmc500_config()
163 dmc->SI1_SI_INTERRUPT_CONTROL = reg_val->SI1_SI_INTERRUPT_CONTROL; in dmc500_config()
164 dmc->SI1_PMU_REQ_CONTROL = reg_val->SI1_PMU_REQ_CONTROL; in dmc500_config()
165 dmc->SI1_PMU_REQ_ATTRIBUTE_MASK_0 = reg_val->SI1_PMU_REQ_ATTRIBUTE_MASK_0; in dmc500_config()
166 dmc->SI1_PMU_REQ_ATTRIBUTE_MATCH_0 = reg_val->SI1_PMU_REQ_ATTRIBUTE_MATCH_0; in dmc500_config()
167 dmc->SI1_PMU_REQ_ATTRIBUTE_MASK_1 = reg_val->SI1_PMU_REQ_ATTRIBUTE_MASK_1; in dmc500_config()
168 dmc->SI1_PMU_REQ_ATTRIBUTE_MATCH_1 = reg_val->SI1_PMU_REQ_ATTRIBUTE_MATCH_1; in dmc500_config()
169 dmc->SI1_PMU_REQ_ATTRIBUTE_MASK_2 = reg_val->SI1_PMU_REQ_ATTRIBUTE_MASK_2; in dmc500_config()
170 dmc->SI1_PMU_REQ_ATTRIBUTE_MATCH_2 = reg_val->SI1_PMU_REQ_ATTRIBUTE_MATCH_2; in dmc500_config()
171 dmc->SI1_PMU_REQ_ATTRIBUTE_MASK_3 = reg_val->SI1_PMU_REQ_ATTRIBUTE_MASK_3; in dmc500_config()
172 dmc->SI1_PMU_REQ_ATTRIBUTE_MATCH_3 = reg_val->SI1_PMU_REQ_ATTRIBUTE_MATCH_3; in dmc500_config()
173 dmc->SI1_THRESHOLD_CONTROL = reg_val->SI1_THRESHOLD_CONTROL; in dmc500_config()
174 dmc->QUEUE_THRESHOLD_CONTROL_31_00 = reg_val->QUEUE_THRESHOLD_CONTROL_31_00; in dmc500_config()
175 dmc->QUEUE_THRESHOLD_CONTROL_63_32 = reg_val->QUEUE_THRESHOLD_CONTROL_63_32; in dmc500_config()
176 dmc->DCB_INTERRUPT_CONTROL = reg_val->DCB_INTERRUPT_CONTROL; in dmc500_config()
177 dmc->PMU_DCB_CONTROL = reg_val->PMU_DCB_CONTROL; in dmc500_config()
178 dmc->PMU_DATA_CONTROL_BLOCK_ATTRIBUTE_MASK_0 = in dmc500_config()
180 dmc->PMU_DATA_CONTROL_BLOCK_ATTRIBUTE_MATCH_0 = in dmc500_config()
182 dmc->PMU_DATA_CONTROL_BLOCK_ATTRIBUTE_MASK_1 = in dmc500_config()
184 dmc->PMU_DATA_CONTROL_BLOCK_ATTRIBUTE_MATCH_1 = in dmc500_config()
186 dmc->PMU_DATA_CONTROL_BLOCK_ATTRIBUTE_MASK_2 = in dmc500_config()
188 dmc->PMU_DATA_CONTROL_BLOCK_ATTRIBUTE_MATCH_2 = in dmc500_config()
190 dmc->PMU_TAG_ENTRIES_ATTRIBUTE_MASK = in dmc500_config()
192 dmc->PMU_TAG_ENTRIES_ATTRIBUTE_MATCH = in dmc500_config()
194 dmc->QE_INTERRUPT_CONTROL = reg_val->QE_INTERRUPT_CONTROL; in dmc500_config()
195 dmc->RANK_TURNAROUND_CONTROL = reg_val->RANK_TURNAROUND_CONTROL; in dmc500_config()
196 dmc->HIT_TURNAROUND_CONTROL = reg_val->HIT_TURNAROUND_CONTROL; in dmc500_config()
197 dmc->QOS_CLASS_CONTROL = reg_val->QOS_CLASS_CONTROL; in dmc500_config()
198 dmc->ESCALATION_CONTROL = reg_val->ESCALATION_CONTROL; in dmc500_config()
199 dmc->QV_CONTROL_31_00 = reg_val->QV_CONTROL_31_00; in dmc500_config()
200 dmc->QV_CONTROL_63_32 = reg_val->QV_CONTROL_63_32; in dmc500_config()
201 dmc->RT_CONTROL_31_00 = reg_val->RT_CONTROL_31_00; in dmc500_config()
202 dmc->RT_CONTROL_63_32 = reg_val->RT_CONTROL_63_32; in dmc500_config()
203 dmc->TIMEOUT_CONTROL = reg_val->TIMEOUT_CONTROL; in dmc500_config()
204 dmc->WRITE_PRIORITY_CONTROL_31_00 = reg_val->WRITE_PRIORITY_CONTROL_31_00; in dmc500_config()
205 dmc->WRITE_PRIORITY_CONTROL_63_32 = reg_val->WRITE_PRIORITY_CONTROL_63_32; in dmc500_config()
206 dmc->DIR_TURNAROUND_CONTROL = reg_val->DIR_TURNAROUND_CONTROL; in dmc500_config()
207 dmc->HIT_PREDICTION_CONTROL = reg_val->HIT_PREDICTION_CONTROL; in dmc500_config()
208 dmc->REFRESH_PRIORITY = reg_val->REFRESH_PRIORITY; in dmc500_config()
209 dmc->MC_UPDATE_CONTROL = reg_val->MC_UPDATE_CONTROL; in dmc500_config()
210 dmc->PHY_UPDATE_CONTROL = reg_val->PHY_UPDATE_CONTROL; in dmc500_config()
211 dmc->PHY_PRIMARY_CONTROL = reg_val->PHY_PRIMARY_CONTROL; in dmc500_config()
212 dmc->LOW_POWER_CONTROL = reg_val->LOW_POWER_CONTROL; in dmc500_config()
213 dmc->PMU_QE_CONTROL = reg_val->PMU_QE_CONTROL; in dmc500_config()
214 dmc->PMU_QE_MUX = reg_val->PMU_QE_MUX; in dmc500_config()
215 dmc->PMU_QOS_ENGINE_ATTRIBUTE_MASK_0 = in dmc500_config()
217 dmc->PMU_QOS_ENGINE_ATTRIBUTE_MATCH_0 = in dmc500_config()
219 dmc->PMU_QOS_ENGINE_ATTRIBUTE_MASK_1 = in dmc500_config()
221 dmc->PMU_QOS_ENGINE_ATTRIBUTE_MATCH_1 = in dmc500_config()
223 dmc->PMU_QOS_ENGINE_ATTRIBUTE_MASK_2 = in dmc500_config()
225 dmc->PMU_QOS_ENGINE_ATTRIBUTE_MATCH_2 = in dmc500_config()
227 dmc->PMU_QUEUED_ENTRIES_ATTRIBUTE_MASK = in dmc500_config()
229 dmc->PMU_QUEUED_ENTRIES_ATTRIBUTE_MATCH = in dmc500_config()
231 dmc->MI_INTERRUPT_CONTROL = reg_val->MI_INTERRUPT_CONTROL; in dmc500_config()
232 dmc->POWER_DOWN_CONTROL = reg_val->POWER_DOWN_CONTROL; in dmc500_config()
233 dmc->REFRESH_CONTROL = reg_val->REFRESH_CONTROL; in dmc500_config()
234 dmc->PMU_MI_CONTROL = reg_val->PMU_MI_CONTROL; in dmc500_config()
235 dmc->PMU_MEMORY_IF_ATTRIBUTE_MASK_0 = in dmc500_config()
237 dmc->PMU_MEMORY_IF_ATTRIBUTE_MATCH_0 = in dmc500_config()
239 dmc->PMU_MEMORY_IF_ATTRIBUTE_MASK_1 = in dmc500_config()
241 dmc->PMU_MEMORY_IF_ATTRIBUTE_MATCH_1 = in dmc500_config()
243 dmc->PMU_BANK_STATES_ATTRIBUTE_MASK = in dmc500_config()
245 dmc->PMU_BANK_STATES_ATTRIBUTE_MATCH = in dmc500_config()
247 dmc->PMU_RANK_STATES_ATTRIBUTE_MASK = in dmc500_config()
249 dmc->PMU_RANK_STATES_ATTRIBUTE_MATCH = in dmc500_config()
251 dmc->CFG_INTERRUPT_CONTROL = reg_val->CFG_INTERRUPT_CONTROL; in dmc500_config()
252 dmc->T_RDDATA_EN = reg_val->T_RDDATA_EN; in dmc500_config()
253 dmc->T_PHYRDLAT = reg_val->T_PHYRDLAT; in dmc500_config()
254 dmc->T_PHYWRLAT = reg_val->T_PHYWRLAT; in dmc500_config()
256 dmc->ERR_RAMECC_CTLR = reg_val->ERR_RAMECC_CTLR; in dmc500_config()
260 dmc->PHY_POWER_CONTROL = reg_val->PHY_POWER_CONTROL; in dmc500_config()
261 dmc->T_PHY_TRAIN = reg_val->T_PHY_TRAIN; in dmc500_config()
262 dmc->PHYUPD_INIT = reg_val->PHYUPD_INIT; in dmc500_config()
264 dmc->PHY_CONFIG = 0x03000000; in dmc500_config()
265 dmc->PHY_CONFIG = 0x0600000A; in dmc500_config()
266 dmc->PHY_CONFIG = 0x01000001; in dmc500_config()
272 dmc->PHY_CONFIG = 0x01000001; in dmc500_config()
273 dmc->PHY_CONFIG = 0x01000000; in dmc500_config()
274 dmc->PHY_CONFIG = 0x00000003; in dmc500_config()
278 module_config->direct_ddr_cmd(dmc); in dmc500_config()
280 dmc->REFRESH_ENABLE = reg_val->REFRESH_ENABLE; in dmc500_config()
295 while ((dmc->MI_STATUS & MOD_DMC500_MI_STATUS_IDLE) != in dmc500_config()
306 dmc->MI_STATE_CONTROL = reg_val->MI_STATE_CONTROL; in dmc500_config()
307 dmc->QUEUE_STATE_CONTROL = reg_val->QUEUE_STATE_CONTROL; in dmc500_config()
308 dmc->SI0_SI_STATE_CONTROL = reg_val->SI0_SI_STATE_CONTROL; in dmc500_config()
309 dmc->SI1_SI_STATE_CONTROL = reg_val->SI1_SI_STATE_CONTROL; in dmc500_config()
313 while ((dmc->QUEUE_STATUS & MOD_DMC500_QUEUE_STATUS_STALL_ACK) != 0) { in dmc500_config()
325 while ((dmc->SI0_SI_STATUS & MOD_DMC500_SI_STATUS_STALL_ACK) != 0) { in dmc500_config()
337 while ((dmc->SI1_SI_STATUS & MOD_DMC500_SI_STATUS_STALL_ACK) != 0) { in dmc500_config()