Lines Matching defs:mod_dmc620_reg
98 struct mod_dmc620_reg { struct
102 FWK_R uint32_t MEMC_STATUS;
103 FWK_R uint32_t MEMC_CONFIG;
104 FWK_W uint32_t MEMC_CMD;
105 uint32_t RESERVED1;
106 FWK_RW uint32_t ADDRESS_CONTROL_NEXT;
107 FWK_RW uint32_t DECODE_CONTROL_NEXT;
108 FWK_RW uint32_t FORMAT_CONTROL;
109 FWK_RW uint32_t ADDRESS_MAP_NEXT;
110 FWK_RW uint32_t LOW_POWER_CONTROL_NEXT;
111 uint32_t RESERVED2;
112 FWK_RW uint32_t TURNAROUND_CONTROL_NEXT;
113 FWK_RW uint32_t HIT_TURNAROUND_CONTROL_NEXT;
114 FWK_RW uint32_t QOS_CLASS_CONTROL_NEXT;
115 FWK_RW uint32_t ESCALATION_CONTROL_NEXT;
116 FWK_RW uint32_t QV_CONTROL_31_00_NEXT;
117 FWK_RW uint32_t QV_CONTROL_63_32_NEXT;
118 FWK_RW uint32_t RT_CONTROL_31_00_NEXT;
119 FWK_RW uint32_t RT_CONTROL_63_32_NEXT;
120 FWK_RW uint32_t TIMEOUT_CONTROL_NEXT;
121 FWK_RW uint32_t CREDIT_CONTROL_NEXT;
122 FWK_RW uint32_t WRITE_PRIORITY_CONTROL_31_00_NEXT;
123 FWK_RW uint32_t WRITE_PRIORITY_CONTROL_63_32_NEXT;
124 FWK_RW uint32_t QUEUE_THRESHOLD_CONTROL_31_00_NEXT;
125 FWK_RW uint32_t QUEUE_THRESHOLD_CONTROL_63_32_NEXT;
126 FWK_RW uint32_t ADDRESS_SHUTTER_31_00_NEXT;
127 FWK_RW uint32_t ADDRESS_SHUTTER_63_32_NEXT;
128 FWK_RW uint32_t ADDRESS_SHUTTER_95_64_NEXT;
129 FWK_RW uint32_t ADDRESS_SHUTTER_127_96_NEXT;
130 FWK_RW uint32_t ADDRESS_SHUTTER_159_128_NEXT;
131 FWK_RW uint32_t ADDRESS_SHUTTER_191_160_NEXT;
132 FWK_RW uint32_t MEMORY_ADDRESS_MAX_31_00_NEXT;
133 FWK_RW uint32_t MEMORY_ADDRESS_MAX_43_32_NEXT;
134 struct mod_dmc620_access_address_next ACCESS_ADDRESS_NEXT
136 FWK_R uint32_t CHANNEL_STATUS;
137 FWK_R uint32_t CHANNEL_STATUS_63_32;
138 FWK_RW uint32_t DIRECT_ADDR;
139 FWK_W uint32_t DIRECT_CMD;
140 FWK_RW uint32_t DCI_REPLAY_TYPE_NEXT;
141 FWK_RW uint32_t DIRECT_CONTROL_NEXT;
142 FWK_RW uint32_t DCI_STRB;
143 FWK_RW uint32_t DCI_DATA;
144 FWK_RW uint32_t REFRESH_CONTROL_NEXT;
145 uint32_t RESERVED3;
146 FWK_RW uint32_t MEMORY_TYPE_NEXT;
147 uint32_t RESERVED4;
148 FWK_RW uint32_t FEATURE_CONFIG;
149 uint32_t RESERVED5;
150 FWK_RW uint32_t NIBBLE_FAILED_031_000;
151 FWK_RW uint32_t NIBBLE_FAILED_063_032;
152 FWK_RW uint32_t NIBBLE_FAILED_095_064;
153 FWK_RW uint32_t NIBBLE_FAILED_127_096;
154 FWK_RW uint32_t QUEUE_ALLOCATE_CONTROL_031_000;
155 FWK_RW uint32_t QUEUE_ALLOCATE_CONTROL_063_032;
156 FWK_RW uint32_t QUEUE_ALLOCATE_CONTROL_095_064;
157 FWK_RW uint32_t QUEUE_ALLOCATE_CONTROL_127_096;
158 uint8_t RESERVED6[0x16C - 0x158];
159 FWK_RW uint32_t LINK_ERR_COUNT;
160 FWK_RW uint32_t SCRUB_CONTROL0_NEXT;
161 FWK_RW uint32_t SCRUB_ADDRESS_MIN0_NEXT;
162 FWK_RW uint32_t SCRUB_ADDRESS_MAX0_NEXT;
163 FWK_R uint32_t SCRUB_ADDRESS_CURRENT0;
164 FWK_RW uint32_t SCRUB_CONTROL1_NEXT;
165 FWK_RW uint32_t SCRUB_ADDRESS_MIN1_NEXT;
166 FWK_RW uint32_t SCRUB_ADDRESS_MAX1_NEXT;
167 FWK_R uint32_t SCRUB_ADDRESS_CURRENT1;
168 uint8_t RESERVED7[0x1A0 - 0x190];
169 FWK_RW uint32_t CS_REMAP_CONTROL_31_00_NEXT;
170 FWK_RW uint32_t CS_REMAP_CONTROL_63_32_NEXT;
171 FWK_RW uint32_t CS_REMAP_CONTROL_95_64_NEXT;
172 FWK_RW uint32_t CS_REMAP_CONTROL_127_96_NEXT;
173 FWK_RW uint32_t CID_REMAP_CONTROL_31_00_NEXT;
174 FWK_RW uint32_t CID_REMAP_CONTROL_63_32_NEXT;
175 uint8_t RESERVED8[0x1C0 - 0x1B8];
176 FWK_RW uint32_t CKE_REMAP_CONTROL_NEXT;
177 FWK_RW uint32_t RST_REMAP_CONTROL_NEXT;
178 FWK_RW uint32_t CK_REMAP_CONTROL_NEXT;
179 uint32_t RESERVED9;
180 FWK_RW uint32_t POWER_GROUP_CONTROL_31_00_NEXT;
181 FWK_RW uint32_t POWER_GROUP_CONTROL_63_32_NEXT;
182 FWK_RW uint32_t POWER_GROUP_CONTROL_95_64_NEXT;
183 FWK_RW uint32_t POWER_GROUP_CONTROL_127_96_NEXT;
184 FWK_RW uint32_t PHY_RDWRDATA_CS_MASK_31_00;
185 FWK_RW uint32_t PHY_RDWRDATA_CS_MASK_63_32;
186 FWK_RW uint32_t PHY_REQUEST_CS_REMAP;
187 uint32_t RESERVED10;
188 FWK_RW uint32_t FEATURE_CONTROL_NEXT;
189 FWK_RW uint32_t MUX_CONTROL_NEXT;
190 FWK_RW uint32_t RANK_REMAP_CONTROL_NEXT;
191 uint32_t RESERVED11;
192 FWK_RW uint32_t T_REFI_NEXT;
193 FWK_RW uint32_t T_RFC_NEXT;
194 FWK_RW uint32_t T_MRR_NEXT;
195 FWK_RW uint32_t T_MRW_NEXT;
196 uint8_t RESERVED12[0x218 - 0x210];
197 FWK_RW uint32_t T_RCD_NEXT;
198 FWK_RW uint32_t T_RAS_NEXT;
199 FWK_RW uint32_t T_RP_NEXT;
200 FWK_RW uint32_t T_RPALL_NEXT;
201 FWK_RW uint32_t T_RRD_NEXT;
202 FWK_RW uint32_t T_ACT_WINDOW_NEXT;
203 uint32_t RESERVED13;
204 FWK_RW uint32_t T_RTR_NEXT;
205 FWK_RW uint32_t T_RTW_NEXT;
206 FWK_RW uint32_t T_RTP_NEXT;
207 uint32_t RESERVED14;
208 FWK_RW uint32_t T_WR_NEXT;
209 FWK_RW uint32_t T_WTR_NEXT;
210 FWK_RW uint32_t T_WTW_NEXT;
211 uint32_t RESERVED15;
212 FWK_RW uint32_t T_XMPD_NEXT;
213 FWK_RW uint32_t T_EP_NEXT;
214 FWK_RW uint32_t T_XP_NEXT;
215 FWK_RW uint32_t T_ESR_NEXT;
216 FWK_RW uint32_t T_XSR_NEXT;
217 FWK_RW uint32_t T_ESRCK_NEXT;
218 FWK_RW uint32_t T_CKXSR_NEXT;
219 FWK_RW uint32_t T_CMD_NEXT;
220 FWK_RW uint32_t T_PARITY_NEXT;
221 FWK_RW uint32_t T_ZQCS_NEXT;
222 FWK_RW uint32_t T_RW_ODT_CLR_NEXT;
223 uint8_t RESERVED16[0x300 - 0x280];
224 FWK_RW uint32_t T_RDDATA_EN_NEXT;
225 FWK_RW uint32_t T_PHYRDLAT_NEXT;
226 FWK_RW uint32_t T_PHYWRLAT_NEXT;
227 uint32_t RESERVED17;
228 FWK_RW uint32_t RDLVL_CONTROL_NEXT;
229 FWK_RW uint32_t RDLVL_MRS_NEXT;
230 FWK_RW uint32_t T_RDLVL_EN_NEXT;
231 FWK_RW uint32_t T_RDLVL_RR_NEXT;
232 FWK_RW uint32_t WRLVL_CONTROL_NEXT;
233 FWK_RW uint32_t WRLVL_MRS_NEXT;
234 FWK_RW uint32_t T_WRLVL_EN_NEXT;
235 FWK_RW uint32_t T_WRLVL_WW_NEXT;
236 uint32_t RESERVED18;
237 FWK_R uint32_t TRAINING_WRLVL_SLICE_STATUS;
238 FWK_R uint32_t TRAINING_RDLVL_SLICE_STATUS;
239 FWK_R uint32_t TRAINING_RDLVL_GATE_SLICE_STATUS;
240 FWK_R uint32_t TRAINING_WDQLVL_SLICE_STATUS;
241 FWK_R uint32_t TRAINING_WDQLVL_SLICE_RESULT;
242 FWK_RW uint32_t PHY_POWER_CONTROL_NEXT;
243 FWK_RW uint32_t T_LPRESP_NEXT;
244 FWK_RW uint32_t PHY_UPDATE_CONTROL_NEXT;
245 FWK_RW uint32_t T_ODTH_NEXT;
246 FWK_RW uint32_t ODT_TIMING_NEXT;
247 uint32_t RESERVED19;
248 FWK_RW uint32_t ODT_WR_CONTROL_31_00_NEXT;
249 FWK_RW uint32_t ODT_WR_CONTROL_63_32_NEXT;
250 FWK_RW uint32_t ODT_RD_CONTROL_31_00_NEXT;
251 FWK_RW uint32_t ODT_RD_CONTROL_63_32_NEXT;
252 FWK_R uint32_t TEMPERATURE_READOUT;
253 uint32_t RESERVED20;
254 FWK_R uint32_t TRAINING_STATUS;
255 FWK_R uint32_t TRAINING_STATUS_63_32;
256 FWK_RW uint32_t DQ_MAP_CONTROL_15_00_NEXT;
257 FWK_RW uint32_t DQ_MAP_CONTROL_31_16_NEXT;
258 FWK_RW uint32_t DQ_MAP_CONTROL_47_32_NEXT;
259 FWK_RW uint32_t DQ_MAP_CONTROL_63_48_NEXT;
260 FWK_RW uint32_t DQ_MAP_CONTROL_71_64_NEXT;
261 uint32_t RESERVED21;
262 FWK_R uint32_t RANK_STATUS;
263 FWK_R uint32_t MODE_CHANGE_STATUS;
264 uint8_t RESERVED22[0x3B0 - 0x3A0];
265 FWK_RW uint32_t ODT_CP_CONTROL_31_00_NEXT;
266 FWK_RW uint32_t ODT_CP_CONTROL_63_32_NEXT;
267 uint8_t RESERVED23[0x400 - 0x3B8];
268 FWK_R uint32_t USER_STATUS;
269 uint32_t RESERVED24;
270 FWK_RW uint32_t USER_CONFIG0_NEXT;
271 FWK_RW uint32_t USER_CONFIG1_NEXT;
272 FWK_RW uint32_t USER_CONFIG2;
273 FWK_RW uint32_t USER_CONFIG3;
274 uint8_t RESERVED25[0x500 - 0x418];
275 FWK_RW uint32_t INTERRUPT_CONTROL;
276 uint32_t RESERVED26;
277 FWK_W uint32_t INTERRUPT_CLR;
278 uint32_t RESERVED27;
279 FWK_R uint32_t INTERRUPT_STATUS;
280 uint8_t RESERVED28[0x538 - 0x514];
281 FWK_R uint32_t FAILED_ACCESS_INT_INFO_31_00;
282 FWK_R uint32_t FAILED_ACCESS_INT_INFO_63_32;
283 FWK_R uint32_t FAILED_PROG_INT_INFO_31_00;
284 FWK_R uint32_t FAILED_PROG_INT_INFO_63_32;
285 FWK_R uint32_t LINK_ERR_INT_INFO_31_00;
286 FWK_R uint32_t LINK_ERR_INT_INFO_63_32;
287 FWK_R uint32_t ARCH_FSM_INT_INFO_31_00;
288 FWK_R uint32_t ARCH_FSM_INT_INFO_63_32;
289 uint8_t RESERVED29[0x610 - 0x558];
290 FWK_RW uint32_t T_DB_TRAIN_RESP_NEXT;
291 FWK_RW uint32_t T_LVL_DISCONNECT_NEXT;
292 uint8_t RESERVED30[0x620 - 0x618];
293 FWK_RW uint32_t WDQLVL_CONTROL_NEXT;
294 FWK_RW uint32_t WDQLVL_VREFDQ_TRAIN_MRS_NEXT;
295 FWK_RW uint32_t WDQLVL_ADDRESS_31_00_NEXT;
296 FWK_RW uint32_t WDQLVL_ADDRESS_63_32_NEXT;
297 FWK_RW uint32_t T_WDQLVL_EN_NEXT;
298 FWK_RW uint32_t T_WDQLVL_WW_NEXT;
299 FWK_RW uint32_t T_WDQLVL_RW_NEXT;
300 FWK_R uint32_t TRAINING_WDQLVL_SLICE_RESP;
301 FWK_R uint32_t TRAINING_RDLVL_SLICE_RESP;
302 uint8_t RESERVED31[0x654 - 0x644];
303 FWK_RW uint32_t PHYMSTR_CONTROL_NEXT;
304 uint8_t RESERVED32[0x700 - 0x658];
305 FWK_R uint32_t ERR0FR;
306 uint32_t RESERVED33;
307 FWK_RW uint32_t ERR0CTLR0;
308 FWK_RW uint32_t ERR0CTLR1;
309 FWK_R uint32_t ERR0STATUS;
310 uint8_t RESERVED34[0x740 - 0x714];
311 FWK_R uint32_t ERR1FR;
312 uint32_t RESERVED35;
313 FWK_R uint32_t ERR1CTLR;
314 uint32_t RESERVED36;
315 FWK_R uint32_t ERR1STATUS;
316 uint32_t RESERVED37;
317 FWK_RW uint32_t ERR1ADDR0;
318 FWK_RW uint32_t ERR1ADDR1;
319 FWK_RW uint32_t ERR1MISC0;
320 FWK_RW uint32_t ERR1MISC1;
321 FWK_RW uint32_t ERR1MISC2;
322 FWK_RW uint32_t ERR1MISC3;
323 FWK_RW uint32_t ERR1MISC4;
324 FWK_RW uint32_t ERR1MISC5;
325 uint8_t RESERVED38[0x780 - 0x778];
326 FWK_R uint32_t ERR2FR;
327 uint32_t RESERVED39;
328 FWK_R uint32_t ERR2CTLR;
329 uint32_t RESERVED40;
330 FWK_R uint32_t ERR2STATUS;
331 uint32_t RESERVED41;
332 FWK_RW uint32_t ERR2ADDR0;
333 FWK_RW uint32_t ERR2ADDR1;
334 FWK_RW uint32_t ERR2MISC0;
335 FWK_RW uint32_t ERR2MISC1;
336 FWK_RW uint32_t ERR2MISC2;
337 FWK_RW uint32_t ERR2MISC3;
338 FWK_RW uint32_t ERR2MISC4;
339 FWK_RW uint32_t ERR2MISC5;
340 uint8_t RESERVED42[0x7C0 - 0x7B8];
341 FWK_R uint32_t ERR3FR;
342 uint32_t RESERVED43;
343 FWK_R uint32_t ERR3CTLR;
344 uint32_t RESERVED44;
345 FWK_R uint32_t ERR3STATUS;
346 uint32_t RESERVED45;
347 FWK_RW uint32_t ERR3ADDR0;
348 FWK_RW uint32_t ERR3ADDR1;
349 uint8_t RESERVED46[0x800 - 0x7E0];
350 FWK_R uint32_t ERR4FR;
351 uint32_t RESERVED47;
352 FWK_R uint32_t ERR4CTLR;
353 uint32_t RESERVED48;
354 FWK_R uint32_t ERR4STATUS;
355 uint32_t RESERVED49;
356 FWK_RW uint32_t ERR4ADDR0;
357 FWK_RW uint32_t ERR4ADDR1;
358 FWK_RW uint32_t ERR4MISC0;
359 FWK_RW uint32_t ERR4MISC1;
360 FWK_RW uint32_t ERR4MISC2;
361 uint8_t RESERVED50[0x840 - 0x82C];
362 FWK_R uint32_t ERR5FR;
363 uint32_t RESERVED51;
364 FWK_R uint32_t ERR5CTLR;
365 uint32_t RESERVED52;
366 FWK_R uint32_t ERR5STATUS;
367 uint32_t RESERVED53;
368 FWK_RW uint32_t ERR5ADDR0;
369 FWK_RW uint32_t ERR5ADDR1;
370 FWK_RW uint32_t ERR5MISC0;
371 FWK_RW uint32_t ERR5MISC1;
372 FWK_RW uint32_t ERR5MISC2;
373 uint8_t RESERVED54[0x880 - 0x86C];
374 FWK_R uint32_t ERR6FR;
375 uint32_t RESERVED55;
376 FWK_R uint32_t ERR6CTLR;
377 uint32_t RESERVED56;
378 FWK_R uint32_t ERR6STATUS;
379 uint32_t RESERVED57;
380 FWK_RW uint32_t ERR6ADDR0;
381 FWK_RW uint32_t ERR6ADDR1;
382 FWK_RW uint32_t ERR6MISC0;
383 FWK_RW uint32_t ERR6MISC1;
384 uint8_t RESERVED58[0x920 - 0x8A8];
385 FWK_RW uint32_t ERRGSR;
386 uint8_t RESERVED59[0xA00 - 0x924];
387 FWK_W uint32_t PMU_SNAPSHOT_REQ;
388 FWK_R uint32_t PMU_SNAPSHOT_ACK;
389 FWK_RW uint32_t PMU_OVERFLOW_STATUS_CLKDIV2;
390 FWK_RW uint32_t PMU_OVERFLOW_STATUS_CLK;
391 struct mod_dmc620_pmu_counter PMC_CLKDIV2_COUNT[8];
392 struct mod_dmc620_pmu_counter PMC_CLK_COUNT[2];
393 uint8_t RESERVED60[0xE00 - 0xBA0];
394 FWK_RW uint32_t INTEG_CFG;
395 uint32_t RESERVED61;
396 FWK_W uint32_t INTEG_OUTPUTS;
397 uint8_t RESERVED62[0x1010 - 0xE0C];
398 FWK_R uint32_t ADDRESS_CONTROL_NOW;
399 FWK_R uint32_t DECODE_CONTROL_NOW;
400 uint32_t RESERVED63;
401 FWK_R uint32_t ADDRESS_MAP_NOW;
402 FWK_R uint32_t LOW_POWER_CONTROL_NOW;
403 uint32_t RESERVED64;
404 FWK_R uint32_t TURNAROUND_CONTROL_NOW;
405 FWK_R uint32_t HIT_TURNAROUND_CONTROL_NOW;
406 FWK_R uint32_t QOS_CLASS_CONTROL_NOW;
407 FWK_R uint32_t ESCALATION_CONTROL_NOW;
408 FWK_R uint32_t QV_CONTROL_31_00_NOW;
409 FWK_R uint32_t QV_CONTROL_63_32_NOW;
410 FWK_R uint32_t RT_CONTROL_31_00_NOW;
411 FWK_R uint32_t RT_CONTROL_63_32_NOW;
412 FWK_R uint32_t TIMEOUT_CONTROL_NOW;
413 FWK_R uint32_t CREDIT_CONTROL_NOW;
414 FWK_R uint32_t WRITE_PRIORITY_CONTROL_31_00_NOW;
415 FWK_R uint32_t WRITE_PRIORITY_CONTROL_63_32_NOW;
416 FWK_R uint32_t QUEUE_THRESHOLD_CONTROL_31_00_NOW;
417 FWK_R uint32_t QUEUE_THRESHOLD_CONTROL_63_32_NOW;
418 FWK_R uint32_t ADDRESS_SHUTTER_31_00_NOW;
419 FWK_R uint32_t ADDRESS_SHUTTER_63_32_NOW;
420 FWK_R uint32_t ADDRESS_SHUTTER_95_64_NOW;
421 FWK_R uint32_t ADDRESS_SHUTTER_127_96_NOW;
422 FWK_R uint32_t ADDRESS_SHUTTER_159_128_NOW;
423 FWK_R uint32_t ADDRESS_SHUTTER_191_160_NOW;
424 FWK_R uint32_t MEMORY_ADDRESS_MAX_31_00_NOW;
425 FWK_R uint32_t MEMORY_ADDRESS_MAX_43_32_NOW;
426 struct mod_dmc620_access_address_now ACCESS_ADDRESS_NOW
428 uint8_t RESERVED65[0x1110 - 0x1100];
429 FWK_R uint32_t DCI_REPLAY_TYPE_NOW;
430 FWK_R uint32_t DIRECT_CONTROL_NOW;
431 uint8_t RESERVED66[0x1120 - 0x1118];
432 FWK_R uint32_t REFRESH_CONTROL_NOW;
433 uint32_t RESERVED67;
434 FWK_R uint32_t MEMORY_TYPE_NOW;
435 uint8_t RESERVED68[0x1170 - 0x112C];
436 FWK_R uint32_t SCRUB_CONTROL0_NOW;
437 FWK_R uint32_t SCRUB_ADDRESS_MIN0_NOW;
438 FWK_R uint32_t SCRUB_ADDRESS_MAX0_NOW;
439 uint32_t RESERVED69;
440 FWK_R uint32_t SCRUB_CONTROL1_NOW;
441 FWK_R uint32_t SCRUB_ADDRESS_MIN1_NOW;
442 FWK_R uint32_t SCRUB_ADDRESS_MAX1_NOW;
443 uint8_t RESERVED70[0x11A0 - 0x118C];
444 FWK_R uint32_t CS_REMAP_CONTROL_31_00_NOW;
445 FWK_R uint32_t CS_REMAP_CONTROL_63_32_NOW;
446 FWK_R uint32_t CS_REMAP_CONTROL_95_64_NOW;
447 FWK_R uint32_t CS_REMAP_CONTROL_127_96_NOW;
448 FWK_R uint32_t CID_REMAP_CONTROL_31_00_NOW;
449 FWK_R uint32_t CID_REMAP_CONTROL_63_32_NOW;
450 uint8_t RESERVED71[0x11C0 - 0x11B8];
451 FWK_R uint32_t CKE_REMAP_CONTROL_31_00_NOW;
452 FWK_R uint32_t RST_REMAP_CONTROL_31_00_NOW;
453 FWK_R uint32_t CK_REMAP_CONTROL_31_00_NOW;
454 FWK_R uint32_t POWER_GROUP_CONTROL_31_00_NOW;
455 FWK_R uint32_t POWER_GROUP_CONTROL_63_32_NOW;
456 FWK_R uint32_t POWER_GROUP_CONTROL_95_64_NOW;
457 FWK_R uint32_t POWER_GROUP_CONTROL_127_96_NOW;
458 uint8_t RESERVED72[0x11F0 - 0x11E0];
459 FWK_R uint32_t FEATURE_CONTROL_NOW;
460 FWK_R uint32_t MUX_CONTROL_NOW;
461 FWK_R uint32_t RANK_REMAP_CONTROL_NOW;
462 uint32_t RESERVED73;
463 FWK_R uint32_t T_REFI_NOW;
464 FWK_R uint32_t T_RFC_NOW;
465 FWK_R uint32_t T_MRR_NOW;
466 FWK_R uint32_t T_MRW_NOW;
467 uint8_t RESERVED74[0x1218 - 0x1210];
468 FWK_R uint32_t T_RCD_NOW;
469 FWK_R uint32_t T_RAS_NOW;
470 FWK_R uint32_t T_RP_NOW;
471 FWK_R uint32_t T_RPALL_NOW;
472 FWK_R uint32_t T_RRD_NOW;
473 FWK_R uint32_t T_ACT_WINDOW_NOW;
474 uint32_t RESERVED75;
475 FWK_R uint32_t T_RTR_NOW;
476 FWK_R uint32_t T_RTW_NOW;
477 FWK_R uint32_t T_RTP_NOW;
478 uint32_t RESERVED76;
479 FWK_R uint32_t T_WR_NOW;
480 FWK_R uint32_t T_WTR_NOW;
481 FWK_R uint32_t T_WTW_NOW;
482 uint32_t RESERVED77;
483 FWK_R uint32_t T_XMPD_NOW;
484 FWK_R uint32_t T_EP_NOW;
485 FWK_R uint32_t T_XP_NOW;
486 FWK_R uint32_t T_ESR_NOW;
487 FWK_R uint32_t T_XSR_NOW;
488 FWK_R uint32_t T_ESRCK_NOW;
489 FWK_R uint32_t T_CKXSR_NOW;
490 FWK_R uint32_t T_CMD_NOW;
491 FWK_R uint32_t T_PARITY_NOW;
492 FWK_R uint32_t T_ZQCS_NOW;
493 FWK_R uint32_t T_RW_ODT_CLR_NOW;
494 uint8_t RESERVED78[0x1300 - 0x1280];
495 FWK_R uint32_t T_RDDATA_EN_NOW;
496 FWK_R uint32_t T_PHYRDLAT_NOW;
497 FWK_R uint32_t T_PHYWRLAT_NOW;
498 uint32_t RESERVED79;
499 FWK_R uint32_t RDLVL_CONTROL_NOW;
500 FWK_R uint32_t RDLVL_MRS_NOW;
501 FWK_R uint32_t T_RDLVL_EN_NOW;
502 FWK_R uint32_t T_RDLVL_RR_NOW;
503 FWK_R uint32_t WRLVL_CONTROL_NOW;
504 FWK_R uint32_t WRLVL_MRS_NOW;
505 FWK_R uint32_t T_WRLVL_EN_NOW;
506 FWK_R uint32_t T_WRLVL_WW_NOW;
507 uint8_t RESERVED80[0x1348 - 0x1330];
508 FWK_R uint32_t PHY_POWER_CONTROL_NOW;
509 FWK_R uint32_t T_LPRESP_NOW;
510 FWK_R uint32_t PHY_UPDATE_CONTROL_NOW;
511 FWK_R uint32_t T_ODTH_NOW;
512 FWK_R uint32_t ODT_TIMING_NOW;
513 uint32_t RESERVED81;
514 FWK_R uint32_t ODT_WR_CONTROL_31_00_NOW;
515 FWK_R uint32_t ODT_WR_CONTROL_63_32_NOW;
516 FWK_R uint32_t ODT_RD_CONTROL_31_00_NOW;
517 FWK_R uint32_t ODT_RD_CONTROL_63_32_NOW;
518 uint8_t RESERVED82[0x1380 - 0x1370];
519 FWK_R uint32_t DQ_MAP_CONTROL_15_00_NOW;
520 FWK_R uint32_t DQ_MAP_CONTROL_31_16_NOW;
521 FWK_R uint32_t DQ_MAP_CONTROL_47_32_NOW;
522 FWK_R uint32_t DQ_MAP_CONTROL_63_48_NOW;
523 FWK_R uint32_t DQ_MAP_CONTROL_71_64_NOW;
524 uint8_t RESERVED83[0x13B0 - 0x1394];
525 FWK_R uint32_t ODT_CP_CONTROL_31_00_NOW;
526 FWK_R uint32_t ODT_CP_CONTROL_63_32_NOW;
527 uint8_t RESERVED84[0x1408 - 0x13B8];
528 FWK_R uint32_t USER_CONFIG0_NOW;
529 FWK_R uint32_t USER_CONFIG1_NOW;
530 uint8_t RESERVED85[0x1610 - 0x1410];
531 FWK_R uint32_t T_DB_TRAIN_RESP_NOW;
532 FWK_R uint32_t T_LVL_DISCONNECT_NOW;
533 uint8_t RESERVED86[0x1620 - 0x1618];
534 FWK_R uint32_t WDQLVL_CONTROL_NOW;
535 FWK_R uint32_t WDQLVL_VREFDQ_TRAIN_MRS_NOW;
536 FWK_R uint32_t WDQLVL_ADDRESS_31_00_NOW;
537 FWK_R uint32_t WDQLVL_ADDRESS_63_32_NOW;
538 FWK_R uint32_t T_WDQLVL_EN_NOW;
539 FWK_R uint32_t T_WDQLVL_WW_NOW;
540 FWK_R uint32_t T_WDQLVL_RW_NOW;
541 uint8_t RESERVED87[0x1654 - 0x163C];
542 FWK_R uint32_t PHYMSTR_CONTROL_NOW;
543 uint8_t RESERVED88[0x1FD0 - 0x1658];
544 FWK_R uint32_t PERIPH_ID_4;
545 uint8_t RESERVED89[0x1FE0 - 0x1FD4];
546 FWK_R uint32_t PERIPH_ID_0;
547 FWK_R uint32_t PERIPH_ID_1;
548 FWK_R uint32_t PERIPH_ID_2;
549 FWK_R uint32_t PERIPH_ID_3;
550 FWK_R uint32_t COMPONENT_ID_0;
551 FWK_R uint32_t COMPONENT_ID_1;
552 FWK_R uint32_t COMPONENT_ID_2;
553 FWK_R uint32_t COMPONENT_ID_3;