Lines Matching refs:dmc
28 static int dmc620_config(struct mod_dmc620_reg *dmc, fwk_id_t ddr_id);
89 struct mod_dmc620_reg *dmc; in dmc620_notify_system_state_transition_resume() local
93 dmc = (struct mod_dmc620_reg *)element_config->dmc; in dmc620_notify_system_state_transition_resume()
95 return dmc620_config(dmc, element_config->ddr_id); in dmc620_notify_system_state_transition_resume()
127 static int dmc620_config(struct mod_dmc620_reg *dmc, fwk_id_t ddr_id) in dmc620_config() argument
136 FWK_LOG_INFO("[DDR] Initialising DMC620 at 0x%x", (uintptr_t)dmc); in dmc620_config()
140 dmc->ADDRESS_CONTROL_NEXT = reg_val->ADDRESS_CONTROL_NEXT; in dmc620_config()
142 dmc->DECODE_CONTROL_NEXT = reg_val->DECODE_CONTROL_NEXT; in dmc620_config()
143 dmc->FORMAT_CONTROL = reg_val->FORMAT_CONTROL; in dmc620_config()
145 dmc->ADDRESS_MAP_NEXT = reg_val->ADDRESS_MAP_NEXT; in dmc620_config()
147 dmc->LOW_POWER_CONTROL_NEXT = reg_val->LOW_POWER_CONTROL_NEXT; in dmc620_config()
148 dmc->TURNAROUND_CONTROL_NEXT = reg_val->TURNAROUND_CONTROL_NEXT; in dmc620_config()
149 dmc->HIT_TURNAROUND_CONTROL_NEXT = reg_val->HIT_TURNAROUND_CONTROL_NEXT; in dmc620_config()
150 dmc->QOS_CLASS_CONTROL_NEXT = reg_val->QOS_CLASS_CONTROL_NEXT; in dmc620_config()
151 dmc->ESCALATION_CONTROL_NEXT = reg_val->ESCALATION_CONTROL_NEXT; in dmc620_config()
152 dmc->QV_CONTROL_31_00_NEXT = reg_val->QV_CONTROL_31_00_NEXT; in dmc620_config()
153 dmc->QV_CONTROL_63_32_NEXT = reg_val->QV_CONTROL_63_32_NEXT; in dmc620_config()
154 dmc->RT_CONTROL_31_00_NEXT = reg_val->RT_CONTROL_31_00_NEXT; in dmc620_config()
155 dmc->RT_CONTROL_63_32_NEXT = reg_val->RT_CONTROL_63_32_NEXT; in dmc620_config()
156 dmc->TIMEOUT_CONTROL_NEXT = reg_val->TIMEOUT_CONTROL_NEXT; in dmc620_config()
157 dmc->CREDIT_CONTROL_NEXT = reg_val->CREDIT_CONTROL_NEXT; in dmc620_config()
158 dmc->WRITE_PRIORITY_CONTROL_31_00_NEXT = in dmc620_config()
160 dmc->WRITE_PRIORITY_CONTROL_63_32_NEXT = in dmc620_config()
162 dmc->QUEUE_THRESHOLD_CONTROL_31_00_NEXT = in dmc620_config()
164 dmc->QUEUE_THRESHOLD_CONTROL_63_32_NEXT = in dmc620_config()
166 dmc->ADDRESS_SHUTTER_31_00_NEXT = reg_val->ADDRESS_SHUTTER_31_00_NEXT; in dmc620_config()
167 dmc->ADDRESS_SHUTTER_63_32_NEXT = reg_val->ADDRESS_SHUTTER_63_32_NEXT; in dmc620_config()
168 dmc->ADDRESS_SHUTTER_95_64_NEXT = reg_val->ADDRESS_SHUTTER_95_64_NEXT; in dmc620_config()
169 dmc->ADDRESS_SHUTTER_127_96_NEXT = reg_val->ADDRESS_SHUTTER_127_96_NEXT; in dmc620_config()
170 dmc->ADDRESS_SHUTTER_159_128_NEXT = reg_val->ADDRESS_SHUTTER_159_128_NEXT; in dmc620_config()
171 dmc->ADDRESS_SHUTTER_191_160_NEXT = reg_val->ADDRESS_SHUTTER_191_160_NEXT; in dmc620_config()
172 dmc->MEMORY_ADDRESS_MAX_31_00_NEXT = reg_val->MEMORY_ADDRESS_MAX_31_00_NEXT; in dmc620_config()
173 dmc->MEMORY_ADDRESS_MAX_43_32_NEXT = reg_val->MEMORY_ADDRESS_MAX_43_32_NEXT; in dmc620_config()
174 dmc->ACCESS_ADDRESS_NEXT[0].MIN_31_00 = in dmc620_config()
176 dmc->ACCESS_ADDRESS_NEXT[0].MIN_43_32 = in dmc620_config()
178 dmc->ACCESS_ADDRESS_NEXT[1].MIN_31_00 = in dmc620_config()
180 dmc->ACCESS_ADDRESS_NEXT[1].MIN_43_32 = in dmc620_config()
182 dmc->ACCESS_ADDRESS_NEXT[2].MIN_31_00 = in dmc620_config()
184 dmc->ACCESS_ADDRESS_NEXT[3].MIN_31_00 = in dmc620_config()
186 dmc->ACCESS_ADDRESS_NEXT[4].MIN_31_00 = in dmc620_config()
188 dmc->ACCESS_ADDRESS_NEXT[5].MIN_31_00 = in dmc620_config()
190 dmc->ACCESS_ADDRESS_NEXT[6].MIN_31_00 = in dmc620_config()
192 dmc->ACCESS_ADDRESS_NEXT[7].MIN_31_00 = in dmc620_config()
195 dmc->DCI_REPLAY_TYPE_NEXT = reg_val->DCI_REPLAY_TYPE_NEXT; in dmc620_config()
196 dmc->DCI_STRB = reg_val->DCI_STRB; in dmc620_config()
197 dmc->DCI_DATA = reg_val->DCI_DATA; in dmc620_config()
198 dmc->REFRESH_CONTROL_NEXT = reg_val->REFRESH_CONTROL_NEXT; in dmc620_config()
199 dmc->MEMORY_TYPE_NEXT = reg_val->MEMORY_TYPE_NEXT; in dmc620_config()
200 dmc->FEATURE_CONFIG = reg_val->FEATURE_CONFIG; in dmc620_config()
201 dmc->FEATURE_CONTROL_NEXT = reg_val->FEATURE_CONTROL_NEXT; in dmc620_config()
202 dmc->MUX_CONTROL_NEXT = reg_val->MUX_CONTROL_NEXT; in dmc620_config()
207 dmc->T_REFI_NEXT = reg_val->T_REFI_NEXT; in dmc620_config()
208 dmc->T_RFC_NEXT = reg_val->T_RFC_NEXT; in dmc620_config()
209 dmc->T_MRR_NEXT = reg_val->T_MRR_NEXT; in dmc620_config()
210 dmc->T_MRW_NEXT = reg_val->T_MRW_NEXT; in dmc620_config()
211 dmc->T_RCD_NEXT = reg_val->T_RCD_NEXT; in dmc620_config()
212 dmc->T_RAS_NEXT = reg_val->T_RAS_NEXT; in dmc620_config()
213 dmc->T_RP_NEXT = reg_val->T_RP_NEXT; in dmc620_config()
214 dmc->T_RPALL_NEXT = reg_val->T_RPALL_NEXT; in dmc620_config()
215 dmc->T_RRD_NEXT = reg_val->T_RRD_NEXT; in dmc620_config()
216 dmc->T_ACT_WINDOW_NEXT = reg_val->T_ACT_WINDOW_NEXT; in dmc620_config()
217 dmc->T_RTR_NEXT = reg_val->T_RTR_NEXT; in dmc620_config()
218 dmc->T_RTW_NEXT = reg_val->T_RTW_NEXT; in dmc620_config()
219 dmc->T_RTP_NEXT = reg_val->T_RTP_NEXT; in dmc620_config()
220 dmc->T_WR_NEXT = reg_val->T_WR_NEXT; in dmc620_config()
221 dmc->T_WTR_NEXT = reg_val->T_WTR_NEXT; in dmc620_config()
222 dmc->T_WTW_NEXT = reg_val->T_WTW_NEXT; in dmc620_config()
223 dmc->T_XMPD_NEXT = reg_val->T_XMPD_NEXT; in dmc620_config()
224 dmc->T_EP_NEXT = reg_val->T_EP_NEXT; in dmc620_config()
225 dmc->T_XP_NEXT = reg_val->T_XP_NEXT; in dmc620_config()
226 dmc->T_ESR_NEXT = reg_val->T_ESR_NEXT; in dmc620_config()
227 dmc->T_XSR_NEXT = reg_val->T_XSR_NEXT; in dmc620_config()
228 dmc->T_ESRCK_NEXT = reg_val->T_ESRCK_NEXT; in dmc620_config()
229 dmc->T_CKXSR_NEXT = reg_val->T_CKXSR_NEXT; in dmc620_config()
230 dmc->T_CMD_NEXT = reg_val->T_CMD_NEXT; in dmc620_config()
231 dmc->T_PARITY_NEXT = reg_val->T_PARITY_NEXT; in dmc620_config()
232 dmc->T_ZQCS_NEXT = reg_val->T_ZQCS_NEXT; in dmc620_config()
233 dmc->T_RW_ODT_CLR_NEXT = reg_val->T_RW_ODT_CLR_NEXT; in dmc620_config()
234 dmc->T_RDDATA_EN_NEXT = reg_val->T_RDDATA_EN_NEXT; in dmc620_config()
235 dmc->T_PHYWRLAT_NEXT = reg_val->T_PHYWRLAT_NEXT; in dmc620_config()
236 dmc->T_PHYRDLAT_NEXT = reg_val->T_PHYRDLAT_NEXT; in dmc620_config()
237 dmc->RDLVL_CONTROL_NEXT = reg_val->RDLVL_CONTROL_NEXT; in dmc620_config()
238 dmc->RDLVL_MRS_NEXT = reg_val->RDLVL_MRS_NEXT; in dmc620_config()
239 dmc->T_RDLVL_EN_NEXT = reg_val->T_RDLVL_EN_NEXT; in dmc620_config()
240 dmc->T_RDLVL_RR_NEXT = reg_val->T_RDLVL_RR_NEXT; in dmc620_config()
241 dmc->WRLVL_CONTROL_NEXT = reg_val->WRLVL_CONTROL_NEXT; in dmc620_config()
242 dmc->WRLVL_MRS_NEXT = reg_val->WRLVL_MRS_NEXT; in dmc620_config()
243 dmc->T_WRLVL_EN_NEXT = reg_val->T_WRLVL_EN_NEXT; in dmc620_config()
244 dmc->T_WRLVL_WW_NEXT = reg_val->T_WRLVL_WW_NEXT; in dmc620_config()
245 dmc->PHY_POWER_CONTROL_NEXT = reg_val->PHY_POWER_CONTROL_NEXT; in dmc620_config()
246 dmc->T_LPRESP_NEXT = reg_val->T_LPRESP_NEXT; in dmc620_config()
247 dmc->PHY_UPDATE_CONTROL_NEXT = reg_val->PHY_UPDATE_CONTROL_NEXT; in dmc620_config()
248 dmc->T_ODTH_NEXT = reg_val->T_ODTH_NEXT; in dmc620_config()
250 dmc->ODT_TIMING_NEXT = reg_val->ODT_TIMING_NEXT; in dmc620_config()
251 dmc->ODT_WR_CONTROL_31_00_NEXT = reg_val->ODT_WR_CONTROL_31_00_NEXT; in dmc620_config()
252 dmc->ODT_WR_CONTROL_63_32_NEXT = reg_val->ODT_WR_CONTROL_63_32_NEXT; in dmc620_config()
253 dmc->ODT_RD_CONTROL_31_00_NEXT = reg_val->ODT_RD_CONTROL_31_00_NEXT; in dmc620_config()
254 dmc->ODT_RD_CONTROL_63_32_NEXT = reg_val->ODT_RD_CONTROL_63_32_NEXT; in dmc620_config()
257 dmc->ERR0CTLR0 = reg_val->ERR0CTLR0; in dmc620_config()
267 module_config->direct_ddr_cmd(dmc); in dmc620_config()
275 dmc->MEMC_CMD = MOD_DMC620_MEMC_CMD_GO; in dmc620_config()
276 dmc->MEMC_CMD = MOD_DMC620_MEMC_CMD_EXECUTE; in dmc620_config()
278 while ((dmc->MEMC_STATUS & MOD_DMC620_MEMC_CMD) != MOD_DMC620_MEMC_CMD_GO) in dmc620_config()