Lines Matching defs:mhu3_mbx_reg
89 struct mhu3_mbx_reg { struct
91 FWK_R uint32_t MHU_BLK_ID;
92 uint8_t RESERVED1[0x10 - 0x04];
93 FWK_R uint32_t MBX_FEAT_SPT0;
94 FWK_R uint32_t MBX_FEAT_SPT1;
95 uint8_t RESERVED2[0x20 - 0x18];
96 FWK_R uint32_t MBX_DBCH_CFG0;
97 uint8_t RESERVED3[0x30 - 0x24];
98 FWK_R uint32_t MBX_FFCH_CFG0;
99 uint8_t RESERVED4[0x40 - 0x34];
100 FWK_R uint32_t MBX_FCH_CFG0;
101 uint8_t RESERVED5[0x50 - 0x44];
102 FWK_R uint32_t MBX_DCH_CFG0;
103 uint8_t RESERVED6[0x100 - 0x54];
104 FWK_RW uint32_t MBX_CTRL;
105 uint8_t RESERVED7[0x140 - 0x104];
106 FWK_RW uint32_t MBX_FCH_CTRL;
107 FWK_RW uint32_t MBX_FCG_INT_EN;
108 uint8_t RESERVED8[0x150 - 0x148];
109 FWK_RW uint32_t MBX_DMA_CTRL;
110 FWK_R uint32_t MBX_DMA_ST;
111 FWK_RW uint64_t MBX_DMA_CDL_BASE;
112 FWK_RW uint32_t MBX_DMA_CDL_PROP;
113 uint8_t RESERVED9[0x400 - 0x164];
114 FWK_R uint32_t MBX_DBCH_INT_ST[(0x410 - 0x400) >> 2];
115 FWK_R uint32_t MBX_FFCH_INT_ST[(0x420 - 0x410) >> 2];
116 FWK_R uint32_t MBX_FCG_INT_ST;
117 uint8_t RESERVED10[0x430 - 0x424];
118 FWK_R uint32_t MBX_FCH_GRP_INT_ST[(0x4B0 - 0x430) >> 2];
119 FWK_R uint32_t MBX_DCH_INT_ST;
120 uint8_t RESERVED11[0xFC8 - 0x4B4];
121 FWK_R uint32_t IIDR;
122 FWK_R uint32_t AIDR;
123 FWK_R uint32_t IMPL_DEF_ID[4 * 11];