Lines Matching refs:fwk_assert
60 fwk_assert(!pl011_ctx.initialized); in mod_pl011_init_ctx()
109 fwk_assert(reg != NULL); in mod_pl011_set_baud_rate()
111 fwk_assert(cfg->baud_rate_bps != 0); in mod_pl011_set_baud_rate()
112 fwk_assert(cfg->clock_rate_hz >= PL011_UARTCLK_MIN); in mod_pl011_set_baud_rate()
113 fwk_assert(cfg->clock_rate_hz <= PL011_UARTCLK_MAX); in mod_pl011_set_baud_rate()
116 fwk_assert((PL011_UARTCLK_MAX * UINT64_C(4)) < UINT32_MAX); in mod_pl011_set_baud_rate()
120 fwk_assert(cfg->baud_rate_bps <= clock_rate_x4); in mod_pl011_set_baud_rate()
128 fwk_assert(divisor_integer <= 0xFFFF); in mod_pl011_set_baud_rate()
131 fwk_assert(divisor_fractional <= 0x3F); in mod_pl011_set_baud_rate()
137 fwk_assert((divisor_integer == 0xFFFF) == (divisor_fractional == 0)); in mod_pl011_set_baud_rate()
151 fwk_assert(ctx->powered); /* Must be powered to enable */ in mod_pl011_enable()
152 fwk_assert(ctx->clocked); /* Must be clocked to enable */ in mod_pl011_enable()
169 fwk_assert(ctx->powered); in mod_pl011_putch()
170 fwk_assert(ctx->clocked); in mod_pl011_putch()
187 fwk_assert(ctx->powered); in mod_pl011_getch()
188 fwk_assert(ctx->clocked); in mod_pl011_getch()
207 fwk_assert(ctx->powered); in mod_pl011_flush()
208 fwk_assert(ctx->clocked); in mod_pl011_flush()
440 fwk_assert(event_params->new_state == MOD_CLOCK_STATE_STOPPED); in mod_pl011_clock_change_pending()
477 fwk_assert(event_params->new_state == MOD_CLOCK_STATE_RUNNING); in mod_pl011_clock_changed()
534 fwk_assert(fwk_id_is_type(event->target_id, FWK_ID_TYPE_ELEMENT)); in mod_pl011_process_notification()
600 fwk_assert(ctx->open); in mod_pl011_io_getch()
619 fwk_assert(ctx->open); in mod_pl011_io_putch()
640 fwk_assert(stream != NULL); /* Validated by the framework */ in mod_pl011_close()
641 fwk_assert(fwk_module_is_valid_element_id(stream->id)); in mod_pl011_close()
646 fwk_assert(ctx->open); in mod_pl011_close()