Lines Matching refs:bits
23 Through various control bits in the ``SCR_EL3`` register, the Arm architecture
26 interrupt routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of
183 - Of the 8 bits of priority that Arm GIC architecture permits, bit 7 must be 0
187 to use the top *n* of the 7 remaining bits to identify and assign interrupts
188 to individual dispatchers. Choosing *n* bits supports up to 2\ :sup:`n`
189 distinct dispatchers. For example, by choosing 2 additional bits (i.e., bits
197 upper bits of the 8 bits are writeable. In the scheme described above, when
198 choosing *n* bits for priority range assignment, the platform must ensure
199 that at least ``n+1`` top bits of GIC priority are writeable.
302 * This platform uses 2 bits for interrupt association. In total, 3 upper
303 * bits are in use.
537 interrupts. This also results in setting the routing bits in ``SCR_EL3``.